IP Library › Granted Patent US 12672584
Granted Patent B2
US 12672584 · App. 17/945,414 · Granted Jun 30, 2026

Semiconductor devices and methods of manufacturing semiconductor devices

Inventors: Kyoung Yeon Lee (Incheon, KR); Jae Beom Shim (Incheon, KR); Byong Jin Kim (Seoul, KR)
Assignee: Amkor Technology Singapore Holding Pte. Ltd.
H10W90/00H01Q1/48H01Q9/0407H10W70/611H10W70/685H10W90/401H10W90/701H10W90/724
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Quick Facts
Patent No.
US 12672584
App. No.
17/945,414
Granted
Jun 30, 2026
Kind
B2
Abstract

In one example, an electronic device comprises a lower substrate comprising a lower dielectric structure and a lower conductive structure, an electronic component coupled with a bottom side of the lower substrate and coupled with the lower conductive structure, an upper substrate over a top side of the lower substrate and comprising an upper dielectric structure and an upper conductive structure, an internal interconnect between the upper substrate and the lower substrate and coupled with the upper conductive structure and the lower conductive structure, and a first antenna component between the upper substrate and the lower substrate and coupled with the upper conductive structure. Other examples and related methods are also disclosed herein.

Claims (75)

1 . An electronic device, comprising:

a lower substrate comprising a lower dielectric structure and a lower conductive structure;

an electronic component coupled with a bottom side of the lower substrate and coupled with the lower conductive structure;

an upper substrate over a top side of the lower substrate and comprising an upper dielectric structure and an upper conductive structure;

an internal interconnect between the upper substrate and the lower substrate and coupled with the upper conductive structure and the lower conductive structure;

a first antenna component between the upper substrate and the lower substrate and coupled with the upper conductive structure; and

an internal encapsulant material between the upper substrate and the lower substrate and contacting the internal interconnect and covering a lateral side of the first antenna component, wherein the first antenna component is inside the internal encapsulant material;

wherein the first antenna component comprises a plurality of component interconnects coupled to the upper conductive structure; and

wherein the plurality of component interconnects are at a first side of the first antenna component facing the upper substrate between the first side of the first antenna component and a bottom side of the upper substrate.

2 . The electronic device of claim 1 , comprising:

a second antenna component over a top side of the upper substrate and coupled with the upper conductive structure.

3 . The electronic device of claim 2 , wherein:

the first antenna component is part of a first array of antenna components on the bottom side of the upper substrate; and

the second antenna component is part of a second array of antenna components on the top side of the upper substrate.

4 . The electronic device of claim 3 , wherein:

the first array of antenna components is offset from the second array of antenna components such that the first antenna component does not overlap the second antenna component.

5 . The electronic device of claim 3 , wherein:

the first array of antenna components comprises a first row of antenna components;

the second array of antenna components comprise a second row of antenna components; and

the first row of antenna components is offset from the second row of antenna components such that the first row of antenna components does not overlap the second row of antenna components.

6 . The electronic device of claim 1 , wherein:

the lower conductive structure comprises an antenna pattern.

7 . The electronic device of claim 1 , wherein:

the internal interconnect comprises a solder-coated metal core ball.

8 . The electronic device of claim 1 , wherein:

the internal encapsulant material has a thickness from about 60 micrometers to about 1020 micrometers;

the first antenna component has a thickness from about 40 micrometers to about 1000 micrometers; and

the thickness of the internal encapsulant material is greater than the thickness of the first antenna component.

9 . The electronic device of claim 1 , wherein:

the upper substrate is a low complexity substrate comprising up to three upper conductive layers;

and the lower substrate is a medium complexity substate comprising up to six lower conductive layers; and

a number of lower conductive layers is greater than a number of upper conductive layers.

10 . The electronic device of claim 1 , comprising:

an external encapsulant below the bottom side of the lower substrate and contacting a lateral side of the electronic component, wherein a bottom side of the electronic component is exposed from the external encapsulant.

11 . The electronic device of claim 1 , comprising:

an external interconnect coupled with the lower conductive structure and having a thickness of about 50 micrometers to about 1000 micrometers;

wherein:

the electronic component has a thickness from about 50 micrometers to about 800 micrometer; and

the thickness of the external interconnect is greater than the thickness of the electronic component.

12 . The electronic device of claim 1 , wherein the plurality of component interconnects comprise solder.

13 . An electronic device, comprising:

a lower substrate comprising a lower dielectric structure and a lower conductive structure;

an electronic component below a bottom side of the lower substrate and coupled with the lower conductive structure; and

an upper substrate over a top side of the lower substrate and comprising an upper dielectric structure and an upper conductive structure, wherein the upper conductive structure comprises an upper antenna pattern comprising a patch antenna;

an internal interconnect between the upper substrate and the lower substrate and coupled with the upper conductive structure and the lower conductive structure;

an internal encapsulant material between the upper substrate and the lower substrate and contacting the internal interconnect; and

an antenna component coupled with the upper conductive structure, wherein the antenna component is inside the internal encapsulant material, wherein the antenna component is coupled with the patch antenna;

wherein the antenna component comprises a plurality of component interconnects coupled to the upper conductive structure; and

wherein the plurality of component interconnects are at a first side of the first antenna component facing the upper substrate between the first side of the antenna component and a bottom side of the upper substrate.

14 . The electronic device of claim 13 , wherein:

the upper antenna pattern is exposed at a top side of the upper substrate.

15 . The electronic device of claim 13 , wherein:

the upper antenna pattern is covered by the upper dielectric structure.

16 . The electronic device of claim 13 , wherein:

the upper conductive structure comprises a ground plane for the patch antenna.

17 . The electronic device of claim 13 , wherein:

the lower conductive structure comprises a ground plane for the patch antenna.

18 . The electronic device of claim 13 , comprising:

an external encapsulant below the bottom side of the lower substrate and contacting a lateral side of the electronic component.

19 . The electronic device of claim 13 , wherein the plurality of component interconnects comprise solder.

20 . A method to manufacture an electronic device, comprising:

providing an upper substrate comprising an upper dielectric structure and an upper conductive structure;

providing a first antenna component coupled with the upper conductive structure;

providing an internal interconnect below a bottom side of the upper substrate and coupled with the upper conductive structure;

providing a lower substrate comprising a lower dielectric structure and a lower conductive structure, wherein the internal interconnect is coupled with the lower conductive structure;

providing an internal encapsulant material between the upper substrate and the lower substrate and contacting the internal interconnect and a lateral side of the first antenna component; and

providing an electronic component coupled with a bottom side of the lower substrate and coupled with the lower conductive structure;

wherein the first antenna component is inside the internal encapsulant material;

wherein the first antenna component comprises a plurality of component interconnects coupled to the upper conductive structure; and

wherein the plurality of component interconnects are at a first side of the first antenna component facing the upper substrate between the first side of the first antenna component and a bottom side of the upper substrate.

21 . The method of claim 20 , comprising:

providing a second antenna component over a top side of the upper substrate and coupled with the upper conductive structure.

22 . The method of claim 20 , comprising:

providing an external encapsulant below the bottom side of the lower substrate and contacting a lateral side of the electronic component.

23 . The method of claim 20 , wherein the plurality of component interconnects comprise solder.