Package comprising an integrated device, a chiplet and a metallization portion

1 . A package comprising:

a substrate comprising at least one dielectric layer and a plurality of interconnects;

a first chiplet coupled to the substrate through a first plurality of solder interconnects,

wherein the first chiplet includes a first front side and a first back side,

wherein the first chiplet includes a first plurality of through substrate vias, and

wherein the first plurality of solder interconnects touch (i) the first plurality of through substrate vias and (ii) interconnects from the plurality of interconnects of the substrate;

a second chiplet coupled to and touching the first chiplet,

wherein the second chiplet includes a second front side and a second back side, and

wherein the second front side of the second chiplet is coupled to and faces in a direction towards the first front side of the first chiplet;

an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet;

a plurality of encapsulation interconnects located in the encapsulation layer;

a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects; and

a first integrated device coupled to the metallization portion.

2 . The package of claim 1 ,

wherein pad interconnects from the first front side of the first chiplet are coupled to and touch pad interconnects from the second front side of the second chiplet.

3 . The package of claim 1 ,

wherein the second chiplet includes a second plurality of through substrate vias.

4 . The package of claim 1 , further comprising a third chiplet coupled to the substrate.

5 . The package of claim 4 , wherein the second chiplet is coupled to and touching the third chiplet.

6 . The package of claim 5 ,

wherein the third chiplet includes a third front side and a third back side,

wherein the third front side of the third chiplet is coupled to and faces in a direction towards the second front side of the second chiplet, and

wherein pad interconnects from the first front side of the first chiplet are coupled to and touch pad interconnects from the second front side of the second chiplet.

7 . The package of claim 6 , wherein the third chiplet includes a deep trench capacitor.

8 . The package of claim 4 , wherein the first chiplet is coupled to and touching the third chiplet.

9 . The package of claim 8 ,

wherein the third chiplet includes a third front side and a third back side,

wherein the third front side of the third chiplet is coupled to and faces in a direction towards the first front side of the first chiplet, and

wherein pad interconnects from the first front side of the first chiplet are coupled to and touch pad interconnects from the third front side of the third chiplet.

10 . The package of claim 1 , wherein an electrical path between the substrate and the first integrated device includes interconnects from the first chiplet and interconnects from the second chiplet.

11 . A package comprising:

a first metallization portion;

a first chiplet coupled to the first metallization portion;

an encapsulation layer coupled to the first metallization portion and the first chiplet;

a plurality of encapsulation interconnects located in the encapsulation layer;

a second metallization portion coupled to the encapsulation layer, the first chiplet, and the plurality of encapsulation interconnects, wherein the first chiplet is located between the first metallization portion and the second metallization portion;

a second chiplet coupled to the second metallization portion, wherein the second metallization portion is located between the first chiplet and the second chiplet; and

a first integrated device coupled to the second chiplet and the second metallization portion such that the second chiplet is located between the first integrated device and the second metallization portion, wherein the first integrated device is coupled to the second chiplet through a first plurality of solder interconnects, wherein the first plurality of solder interconnects touches (i) interconnects from the first integrated device and (ii) interconnects from the second chiplet.

12 . The package of claim 11 ,

wherein the first chiplet includes a first front side and a first back side,

wherein the second chiplet includes a second front side and a second back side, and

wherein the first back side of the first chiplet is coupled to the second metallization portion through a second plurality of solder interconnects, and

wherein the second front side of the second chiplet is coupled to and touch the second metallization portion.

13 . The package of claim 11 , wherein the first chiplet and the second chiplet are configured to be coupled to a power distribution network.

14 . A device comprising:

a package comprising:

a substrate comprising at least one dielectric layer and a plurality of interconnects;

a bridge located at least partially in the substrate, wherein the bridge comprises:

a bridge substrate;

a plurality of bridge interconnects; and

a bridge dielectric layer;

a first chiplet coupled to the substrate and the bridge,

wherein a first set of solder interconnects from a first plurality of solder interconnects touch the first chiplet and a first set of interconnects from the substrate, and

wherein a second set of solder interconnects from the first plurality of solder interconnects touch the first chiplet and a first set of bridge interconnects from the bridge;

a second chiplet coupled to the substrate and the bridge,

wherein a first set of solder interconnects from a second plurality of solder interconnects touch the second chiplet and a second set of interconnects from the substrate, and

wherein a second set of solder interconnects from the second plurality of solder interconnects touch the second chiplet and a second set of bridge interconnects from the bridge;

an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet;

a plurality of encapsulation interconnects located in the encapsulation layer, wherein at least one encapsulation interconnect is coupled to and touches a bridge interconnect from the bridge;

a metallization portion coupled to the encapsulation layer and the plurality of encapsulation interconnects; and

a first integrated device coupled to the metallization portion.

15 . The device of claim 14 ,

wherein the first chiplet includes a first front side and a first back side, and

wherein the first front side of the first chiplet is coupled to the bridge located at least partially in the substrate through the first set of solder interconnects from the first plurality of solder interconnects.

16 . The device of claim 14 , wherein at least one other encapsulation interconnect from the plurality of encapsulation interconnects is coupled to the first back side of the first chiplet.

17 . The device of claim 14 , wherein at least one other encapsulation interconnect from the plurality of encapsulation interconnects is coupled to a back side of the second chiplet.

18 . The device of claim 14 , wherein the first chiplet is configured to be coupled to a power distribution network.

19 . The device of claim 14 , wherein the first chiplet and/or the second chiplet includes a deep trench capacitor.

20 . The device of claim 14 , wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.