IP Library Granted Patent US 12672591
Granted Patent B2
US 12672591 · App. 18/662,749 · Granted Jun 30, 2026

Vertically stacked semiconductor device including a hybrid bond contact junction circuit and methods for forming the same

Inventors: Jen-Yuan Chang (Hsinchu, TW); Chia-Ping Lai (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H10W90/00H10W20/40H10W80/312H10W80/327H10W90/792
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12672591
App. No.
18/662,749
Granted
Jun 30, 2026
Kind
B2
Abstract

A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.

Claims (35)

1 . A method of making a junction circuit, the method comprising:

forming a metal via on a side surface of a top die;

forming a metal layer on the metal via, wherein the metal via is located at a first end of the metal layer; and

forming a metal pad on the metal layer, wherein the metal pad is located at a second end of the metal layer opposite the first end of the metal layer, and is configured to contact a bottom die.

2 . The method of claim 1 , wherein the forming of the metal via comprises forming the metal via to have a substantially circular cross-section.

3 . The method of claim 1 , wherein the side surface of the top die comprises a top die contact and the forming of the metal via comprises forming the metal via in contact with the top die contact.

4 . The method of claim 1 , wherein the forming of the metal layer comprises forming the metal layer to have a thickness substantially the same as a thickness of the metal via.

5 . The method of claim 1 , wherein the forming of the metal layer comprises forming the metal layer to extend longitudinally in a first direction and to have a length in the first direction greater than a diameter of the metal via in the first direction.

6 . The method of claim 5 , wherein the side surface of the top die comprises an exposed dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric, and the forming of the metal layer comprises forming the metal layer to extend longitudinally in the first direction over the exposed dielectric layer.

7 . The method of claim 5 , wherein the forming of the metal layer comprises forming the metal layer to have a length in a second direction perpendicular to the first direction greater than the diameter of the metal via.

8 . The method of claim 7 , wherein the forming of the metal pad comprises forming the metal pad to have a length in the first direction less than the length of the metal layer in the first direction and to have a length in the second direction greater than the length of the metal layer in the second direction.

9 . The method of claim 1 , wherein the forming of the metal pad comprises forming the metal pad to have a thickness substantially the same as a thickness of the metal layer and substantially the same as a thickness of the metal via.

10 . A method of coupling a first semiconductor die to a second semiconductor die, the method comprising:

removing a portion of the second semiconductor die to expose a second contact in a side surface of the second semiconductor die;

forming a junction circuit on the second contact in the side surface of the second semiconductor die; and

attaching the first semiconductor die to the side surface of the second semiconductor die such that the junction circuit contacts a first contact in the first semiconductor die.

11 . The method of claim 10 , wherein the removing of the portion of the second semiconductor die comprises performing at least one of grinding or chemical mechanical polishing (CMP) to expose the second contact.

12 . The method of claim 10 , wherein the removing of the portion of the second semiconductor die comprises exposing a dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric in the side surface of the second semiconductor die, and the second contact is in the exposed dielectric layer.

13 . The method of claim 12 , wherein the forming of the junction circuit comprises forming the junction circuit to include a metal layer, a metal via at a first end of the metal layer and a metal pad at a second end of the metal layer opposite the first end.

14 . The method of claim 13 , wherein the forming of the junction circuit comprises forming the junction circuit such that the metal layer extends longitudinally in a first direction over the exposed dielectric layer.

15 . The method of claim 10 , wherein the attaching of the first semiconductor die to the side surface of the second semiconductor die comprises attaching the first semiconductor die to the side surface of the second semiconductor die such that the first semiconductor die is substantially perpendicular to the second semiconductor die.

16 . The method of claim 10 , wherein the forming of the junction circuit comprises forming the junction circuit in a bonding layer and the attaching of the first semiconductor die to the side surface of the second semiconductor die comprises bonding the first semiconductor die to the side surface of the second semiconductor die with the bonding layer.

17 . The method of claim 10 , wherein the second semiconductor die comprises a plurality of second semiconductor dies,

wherein the removing of the portion of the second semiconductor die comprises removing a portion of the plurality of second semiconductor dies to expose a plurality of second contacts in a side surface of the plurality of second semiconductor dies,

wherein the forming of the junction circuit comprises forming a plurality of the junction circuits on the plurality of second contacts in the side surface of the plurality of second semiconductor dies, respectively, and

wherein the attaching of the first semiconductor die to the side surface of the second semiconductor die comprises attaching the first semiconductor die to the side surface of the plurality of second semiconductor dies such that the plurality of junction circuits contacts a plurality of first contacts in the first semiconductor die, respectively.

18 . A method of coupling a first semiconductor die to a second semiconductor die, the method comprising:

forming a bonding layer on a side surface of the second semiconductor die;

forming a junction circuit in the bonding layer, wherein the junction circuit contacts a second contact in the second semiconductor die; and

attaching the first semiconductor die to the bonding layer such that the first semiconductor die is perpendicular to the second semiconductor die, wherein the junction circuit contacts a first contact in the first semiconductor die.

19 . The method of claim 18 , wherein the forming of the bonding layer comprises forming a plurality of dielectric layers and the forming of the junction circuit comprises forming a plurality of portions of the junction circuit in the plurality of dielectric layers, respectively.

20 . The method of claim 18 , wherein the second semiconductor die comprises a plurality of second semiconductor dies,

wherein the forming of the bonding layer comprises forming the bonding layer on the plurality of second semiconductor dies,

wherein the forming of the junction circuit comprises forming a plurality of junction circuits in the bonding layer, and

wherein the attaching of the first semiconductor die to the bonding layer comprises attaching the first semiconductor die to the bonding layer such that the plurality of junction circuits contacts a plurality of first contacts in the first semiconductor die, respectively.