IP Library Granted Patent US 12674244
Granted Patent B2
US 12674244 · App. 18/160,912 · Granted Jul 7, 2026

Low temperature hybrid bonding metallization

Inventors: Jing Xu (Kalispell, MT); John Klocke (Kalispell, MT)
Assignee: APPLIED Materials, Inc.
C25D3/38C25D5/02C25D5/10C25D5/34C25D7/12H10P90/00H10W20/057
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Quick Facts
Patent No.
US 12674244
App. No.
18/160,912
Granted
Jul 7, 2026
Kind
B2
Abstract

A semiconductor wafer, including a substrate, at least one via formed in the substrate, and copper electroplating inside the at least one via, where the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper. Further, a method of making a semiconductor wafer, the method comprising providing a substrate; etching the substrate to form at least one via; and depositing copper electroplating inside the at least one via, wherein the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper.

Claims (26)

1 . A semiconductor wafer, comprising:

a substrate;

at least one via formed in the substrate; and

a copper electroplating inside the at least one via, wherein the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper, wherein the bulk copper is fine grain copper.

2 . The semiconductor of claim 1 , wherein the first layer is deposited in the at least one via before the second layer is deposited in the via.

3 . The semiconductor of claim 2 , wherein the first layer extends above a top of the at least one via.

4 . The semiconductor of claim 1 , wherein the second layer is deposited in the via before the first layer is deposited in the at least one via.

5 . The semiconductor of claim 4 , wherein the second layer extends above a top of the at least one via.

6 . The semiconductor wafer of claim 4 , wherein the first layer of nanotwin copper provides a hybrid bonding interface, wherein the hybrid bonding interface comprises above 50% nanotwin copper.

7 . The semiconductor of claim 1 , wherein the second layer partially fills the at least one via; and the first layer partially fills the at least one via and extends above a top of the at least one via.

8 . The semiconductor wafer of claim 1 , wherein an aspect ratio of the at least one via and the substrate is about 0.1.

9 . A method of making a semiconductor wafer, the method comprising:

providing a substrate;

etching the substrate to form at least one via;

depositing a first layer of nanotwin copper inside the at least one via; and

depositing a second layer of bulk copper inside the at least one via, wherein the second layer of bulk copper is a fine grain copper.

10 . The method of claim 9 , wherein the first layer of nanotwin copper is deposited before depositing the second layer of bulk copper.

11 . The method of claim 9 , wherein the first layer of nanotwin copper extends above a top of the at least one via.

12 . The method of claim 9 , wherein the second layer of bulk copper is deposited before depositing the first layer of nanotwin copper.

13 . The method of claim 12 , wherein the second layer of bulk copper extends above a top of the at least one via.

14 . The method of claim 12 , wherein the method further comprises:

forming a hybrid bonding interface between the first layer of nanotwin copper and the second layer of bulk copper.

15 . The method of claim 14 , wherein the hybrid bonding interface comprises above 50% nanotwin copper.

16 . The method of claim 12 , further comprising:

after depositing the second layer of bulk copper, cleaning the second layer of bulk copper by applying an acid before depositing the first layer of nanotwin copper.

17 . The method of claim 16 , wherein cleaning the second layer of bulk copper further comprises applying an oxidizing agent.