Wireless circuitry with low-noise peak detection
An electronic device may include an antenna, a receiver, and a transmission line path that couples the antenna to the receiver. A peak detector may receive a radio-frequency signal from the transmission line path and may output a DC voltage indicative of a peak voltage level of the signal. The peak detector may include a pair of square law transistors having source-drain terminals coupled to an output of the peak detector. The peak detector may include a differential pair of transistors coupled between a power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and gate terminals of the square law transistors. The diode-connected transistors may cause noise current to flow along feedback loop paths from the source-drain terminals onto the gate terminals of the square law transistors. This may remove noise from the output of the peak detector.
1 . A voltage peak detector having an input terminal and a differential output, the voltage peak detector comprising:
a first transistor having a first gate terminal communicatively coupled to the input terminal, having a first source-drain terminal coupled to a first output terminal of the differential output, and having a second source-drain terminal communicatively coupled to a ground;
a second transistor having a third source-drain terminal coupled to a power supply voltage and having a fourth source-drain terminal coupled to the first output terminal;
a diode-connected transistor having a fifth source-drain terminal coupled to the first output terminal and having a sixth source-drain terminal coupled to the first gate terminal, wherein the diode-connected transistor has a second gate terminal that is connected to the fifth source-drain terminal;
a third transistor having a second gate terminal coupled to a first circuit node, having a seventh source-drain terminal coupled to a second output terminal of the differential output, and having an eighth source-drain terminal communicatively coupled to the ground;
a fourth transistor having a ninth source-drain terminal coupled to the power supply voltage and having a tenth source-drain terminal coupled to the second output terminal, wherein the second transistor has a third gate terminal coupled to a second circuit node and the fourth transistor has a fourth gate terminal coupled to the second circuit node;
a first resistor coupled in series between the second circuit node and the first output terminal;
a second resistor coupled in series between the second circuit node and the second output terminal;
a fifth transistor having a fifth gate terminal, having an eleventh source-drain terminal coupled to the fifth gate terminal, and having a twelfth source-drain terminal, wherein the twelfth source-drain terminal is coupled to the ground;
a third resistor coupled in series between the eleventh source-drain terminal and the first gate terminal; and
a fourth resistor coupled in series between the eleventh source-drain terminal and the first circuit node.
2 . The voltage peak detector of claim 1 , wherein the diode-connected transistor is configured to pass a noise current from the fifth source-drain terminal onto the first gate terminal.
3 . The voltage peak detector of claim 2 , wherein the first transistor is configured to pass the noise current between the first source-drain terminal and the second source-drain terminal, the noise current as passed by the diode-connected transistor onto the first gate terminal being an inversion of the noise current as passed between the first source-drain terminal and the second source-drain terminal.
4 . The voltage peak detector of claim 1 , further comprising:
an additional diode-connected transistor having a thirteenth source-drain terminal coupled to the second output terminal, having a fourteenth source-drain terminal coupled to the first circuit node, and having a sixth gate terminal connected to the thirteenth source-drain terminal.
5 . The voltage peak detector of claim 1 , further comprising:
an additional diode-connected transistor having an eleventh source-drain terminal coupled to the second output terminal and having a twelfth source-drain terminal coupled to the first circuit node.
6 . The voltage peak detector of claim 1 , wherein the first transistor and the third transistor are square law devices.
7 . Wireless circuitry comprising:
a radio-frequency transmission line path configured to convey a radio-frequency signal;
an analog-to-digital converter (ADC);
a peak detector having an output communicatively coupled to the ADC, wherein the peak detector includes
a differential pair of transistors coupled between a power supply voltage and the output,
a first transistor having a first gate terminal configured to receive the radio-frequency signal from the radio-frequency transmission line path and having a first source-drain terminal coupled to the output, and
a second transistor having a second source-drain terminal coupled to the output and the first source-drain terminal, having a second gate terminal coupled to the second source-drain terminal, and having a third source-drain terminal coupled to the first gate terminal;
a third transistor having a third gate terminal and having a fourth source-drain terminal, the fourth source-drain terminal being coupled to the output;
a fourth transistor having a fifth source-drain terminal coupled to the output and the fourth source-drain terminal, having a fourth gate terminal coupled to the fifth source-drain terminal, and having a sixth source-drain terminal coupled to the third gate terminal; and
a fifth transistor having a seventh source-drain terminal communicatively coupled to the first gate terminal and the third gate terminal and having a fifth gate terminal coupled to the seventh source-drain terminal.
8 . The wireless circuitry of claim 7 , wherein the peak detector is configured to generate a DC voltage at the output based on the radio-frequency signal, the ADC being configured to generate a digital value based on the DC voltage.
9 . The wireless circuitry of claim 8 , wherein the radio-frequency signals are in a satellite navigation band and the wireless circuitry further comprises one or more processors configured to mitigate a jammer signal in response to the digital value exceeding a threshold value.
10 . A voltage peak detector having an input terminal and a differential output, the voltage peak detector comprising:
a first transistor having a first gate terminal communicatively coupled to the input terminal, having a first source-drain terminal coupled to a first output terminal of the differential output, and having a second source-drain terminal communicatively coupled to a ground;
a second transistor having a third source-drain terminal coupled to a power supply voltage and having a fourth source-drain terminal coupled to the first output terminal;
a diode-connected transistor having a fifth source-drain terminal coupled to the first output terminal and having a sixth source-drain terminal coupled to the first gate terminal; and
a third transistor, wherein the third transistor has a seventh source-drain terminal communicatively coupled to the first gate terminal and the sixth source-drain terminal; and
a fourth transistor having a second gate terminal, an eighth source-drain terminal coupled to a second output terminal of the differential output, and a ninth source-drain terminal communicatively coupled to the ground, wherein the seventh source-drain terminal is communicatively coupled to the second gate terminal.
11 . The voltage peak detector of claim 10 , wherein the third transistor has a tenth source-drain terminal coupled to the ground.
12 . The voltage peak detector of claim 10 , wherein the third transistor has a third gate terminal coupled to the seventh source-drain terminal.