Measuring device for capacitance of semiconductor device and measurement jig
To improve the measurement accuracy of feedback capacitance of a semiconductor device. Between a gate terminal of a semiconductor device subject to measurement and an Lc terminal of an LCR meter, a first wiring that is passed through a core of a transformer once and connected between a gate terminal and a source terminal and a second wiring wound N times around a core of the transformer, and one end is connected to the Lc terminal and the other end is grounded are provided. when ω represents an angular frequency of the AC signal applied to the drain terminal of the semiconductor device, L S_6A represents inductance of the first wiring, L S_6B represents inductance of the second wiring, and C GS represents gate-source parasitic capacitance of the semiconductor device, a relationship of ωL S_6A <1/(ωC GS ), and ωL S_6B /N 2 <1/(ωC GS ) are satisfied.
1 . A measuring device configured to measure capacitance of a three-terminal semiconductor device, comprising an LCR meter that includes an Hc terminal that outputs an AC signal, an Lc terminal that monitors current, an Hp terminal and an Lp terminal that monitor voltage, and a GND terminal, wherein
a drain terminal of the semiconductor device subject to measurement is connected to the Hc terminal and the Hp terminal,
a gate terminal of the semiconductor device is connected to the Lp terminal, and
a source terminal of the semiconductor device is connected to the GND terminal,
the measuring device further comprising:
a first transformer;
a first wiring that is passed through a core of the first transformer only once and connected between the gate terminal and the source terminal of the semiconductor device; and
a second wiring that is wound N times around the core of the first transformer, one end of which is connected to the Lc terminal, and another end of which is grounded during measurement, wherein
when ω represents an angular frequency of the AC signal, L S_6A represents inductance of the first wiring, L S_6B represents inductance of the second wiring, and Cos represents gate-source parasitic capacitance of the semiconductor device,
a relationship of
ω L S_6A <1/(ω C GS ), and
ω L S_6B /N 2 <1/(ω C GS )
are satisfied.
2 . The measuring device for capacitance of the semiconductor device according to claim 1 , wherein
ωL S_6A +ωL S_6B /N 2 is less than 5% of 1/(ωC GS ).
3 . The measuring device for capacitance of the semiconductor device according to claim 1 , wherein
at least one of the wirings that is passed through the core of the transformer only once is a litz wire.
4 . The measuring device for capacitance of the semiconductor device according to claim 1 , wherein
the drain terminal of the semiconductor device is connected to a power supply via a first choke coil, to the Hc terminal via a first block capacitor, and to the HP terminal via a second block capacitor, respectively, and
the source terminal of the semiconductor device is grounded via a second choke coil.
5 . A measuring device configured to measure capacitance of a three-terminal semiconductor device, comprising an LCR meter that includes an Hc terminal that outputs an AC signal, an Lc terminal that monitors current, an Hp terminal and an Lp terminal that monitor voltage, and a GND terminal, wherein
a drain terminal of the semiconductor device subject to measurement is connected to the Hc terminal and the Hp terminal,
a gate terminal of the semiconductor device is connected to the Lp terminal, and
a source terminal of the semiconductor device is connected to the GND terminal,
the measuring device further comprising:
a first transformer;
a second transformer;
a first wiring that is passed through a core of the first transformer only once and connected between the gate terminal and the source terminal of the semiconductor device;
a second wiring that is wound N times around each of the core of the first transformer and a core of the second transformer, and both ends of which are grounded during measurement; and
a third wiring that passes through the core of the second transformer once, one end of which is connected to the Lc terminal, and another end of which is grounded during measurement, wherein
when ω represents an angular frequency of the AC signal, L S_6C represents inductance of the third wiring, and C GS represents gate-source parasitic capacitance of the semiconductor device,
a relationship of
L S_6C <1/(ω C GS )
is satisfied.
6 . The measuring device for capacitance of the semiconductor device according to claim 5 , wherein
when L S_6A represents inductance of the first wiring, and L S_6B represents inductance of the second wiring, ωL S_6A +ωL S_6B /N 2 +ωL S_6C is less than 5% of 1/(ωC GS ).
7 . The measuring device for capacitance of the semiconductor device according to claim 5 , wherein
at least one of the wirings that is passed through the core of the transformer only once is a litz wire.
8 . The measuring device for capacitance of the semiconductor device according to claim 5 , wherein
the drain terminal of the semiconductor device is connected to a power supply via a first choke coil, to the Hc terminal via a first block capacitor, and to the HP terminal via a second block capacitor, respectively, and
the source terminal of the semiconductor device is grounded via a second choke coil.
9 . A measuring device configured to measure capacitance of a three-terminal semiconductor device, comprising an LCR meter that includes an Hc terminal that outputs an AC signal, an Lc terminal that monitors current, an Hp terminal and an Lp terminal that monitor voltage, and a GND terminal, wherein
a drain terminal of the semiconductor device subject to measurement is connected to the Hc terminal and the Hp terminal,
a gate terminal of the semiconductor device is connected to the Lp terminal, and
a source terminal of the semiconductor device is connected to the GND terminal,
the measuring device further comprising:
a first transformer;
a second transformer;
a third transformer;
a first wiring that is passed through a core of the first transformer only once and connected between the gate terminal and the source terminal of the semiconductor device;
a second wiring having a ring-shape passed through each of the core of the first transformer and the core of the second transformer once;
a third wiring that is wound N times around each of the core of the second transformer and a core of the third transformer, and both ends of which are grounded during measurement; and
a fourth wiring that passes through the core of the third transformer once, one end of which is connected to the Lc terminal, and another end of which is grounded during measurement, wherein
when ω represents an angular frequency of the AC signal, L S_6B represents inductance of the second wiring, L S_6D represents inductance of the third wiring, and Cos represents gate-source parasitic capacitance of the semiconductor device,
a relationship of
ω L S_6B <<1/(ω C GS ), and
ω L S_6D /N 2 <1/(ω C GS )
are satisfied.
10 . The measuring device for capacitance of the semiconductor device according to claim 9 , wherein
when L S_6A represents inductance of the first wiring, and L S_6C represents inductance of the fourth wiring, ωL S_6A +ωL S_6B +ωL S_6D /N 2 +ωL S_6C is less than 5% of 1/(ωC GS ).
11 . The measuring device for capacitance of the semiconductor device according to claim 9 , wherein
at least one of the wirings that is passed through the core of the transformer only once is a litz wire.
12 . The measuring device for capacitance of the semiconductor device according to claim 9 , wherein
the drain terminal of the semiconductor device is connected to a power supply via a first choke coil, to the Hc terminal via a first block capacitor, and to the HP terminal via a second block capacitor, respectively, and
the source terminal of the semiconductor device is grounded via a second choke coil.