Semiconductor device including switch control circuit that controls switches based on test setting signal and method of manufacturing the same

1 . A semiconductor device comprising:

a terminal circuit including a first external terminal and a second external terminal, wherein the first external terminal is configured to receive a test input signal from an external inspection device;

a core unit that includes a first internal circuit provided corresponding to the first external terminal and a second internal circuit provided corresponding to the second external terminal, and performs signal processing, using at least one of the first internal circuit and the second internal circuit, on the test input signal received by at least one of the first internal circuit and the second internal circuit via the first external terminal to generate a test output signal, the test output signal being output to the external inspection device via the first external terminal;

a switch circuit disposed on a wiring path between the terminal circuit and the core unit, wherein, when the external inspection device is connected to the first external terminal, the switch circuit selectively connects the first external terminal to the first internal circuit, the second internal circuit, or both the first internal circuit and the second internal circuit; and

a switch control circuit that receives a test setting signal from the external inspection device and controls ON and OFF of one or more switches included in the switch circuit based on the test setting signal to select a connection destination of the external inspection device in the switch circuit.

2 . The semiconductor device according to claim 1 ,

wherein the test setting signal is a serial signal, and

wherein the switch control circuit selects the connection destination of the external inspection device based on a time-series pattern of the serial signal.

3 . The semiconductor device according to claim 1 ,

wherein the test setting signal is a plurality of voltage signals, and

wherein the switch control circuit selects the connection destination of the external inspection device based on a combination of a plurality of voltage values indicated by the plurality of voltage signals.

4 . The semiconductor device according to claim 1 , wherein the one or more switches in the switch circuit include:

a first switch that connects the first external terminal and the first internal circuit;

a second switch that connects the second external terminal and the second internal circuit; and

a third switch that connects the first external terminal and the second external terminal.

5 . The semiconductor device according to claim 4 , wherein the switch circuit controls the first switch and the second switch to be on and controls the third switch to be off in a case where the semiconductor device is operated normally.

6 . The semiconductor device according to claim 4 , further comprising:

a first input buffer that receives an input signal from the terminal circuit and outputs the input signal to the first internal circuit; and

a second input buffer that receives an input signal from the terminal circuit and outputs the input signal to the second internal circuit,

wherein the first switch is inserted into an input node of the first input buffer, and

wherein the second switch is inserted into an input node of the second input buffer.

7 . The semiconductor device according to claim 4 , further comprising:

a first tristate input buffer that receives an input signal from the terminal circuit, outputs the input signal to the first internal circuit, and is controlled to be on/off by a first input control signal; and

a second tristate input buffer that receives an input signal from the terminal circuit, outputs the input signal to the second internal circuit, and is controlled to be on/off by a second input control signal,

wherein the first switch is realized by the first tristate input buffer,

wherein the second switch is realized by the second tristate input buffer, and

wherein the switch control circuit fixes the first input control signal to be an off level when the external inspection device is connected to the second internal circuit.

8 . The semiconductor device according to claim 1 , further comprising:

a first tristate input buffer that receives an input signal from the first external terminal, outputs the input signal to the core unit, and is controlled to be on/off by a first post-stage input control signal; and

a second tristate input buffer that receives an input signal from the second external terminal, outputs the input signal to the core unit, and is controlled to be on/off by a second post-stage input control signal,

wherein the first internal circuit outputs a first pre-stage input control signal and receives a first post-stage input signal associated with the first pre-stage input control signal,

wherein the second internal circuit outputs a second pre-stage input control signal and receives a second post-stage input signal associated with the second pre-stage input control signal, and

wherein, when the external inspection device is connected to the second internal circuit, the switch control circuit connects the second pre-stage input control signal to the first post-stage input control signal, and connects a first pre-stage input signal from the first tristate input buffer to the second post-stage input signal.

9 . The semiconductor device according to claim 1 ,

wherein the terminal circuit includes three or more external terminals including the first external terminal and the second external terminal,

wherein the core unit includes three or more internal circuits including the first internal circuit and the second internal circuit, and

wherein the switch circuit connects the external inspection device to any one or all of the three or more internal circuits in a state where the external inspection device is connected to the first external terminal.

10 . A method of manufacturing a semiconductor device, the method comprising:

a pre-process of forming a plurality of semiconductor devices on a semiconductor wafer;

a wafer test process of testing the plurality of semiconductor devices using a probe inspection device;

an assembly process of separating the plurality of semiconductor devices individually from the semiconductor wafer and packaging the individually separated plurality of semiconductor devices; and

a final test process of testing the assembled plurality of semiconductor devices using a semiconductor inspection device,

wherein the pre-process includes forming, in each of the plurality of semiconductor devices:

a terminal circuit including a first external terminal and a second external terminal, wherein the first external terminal is configured to receive a test input signal from an external inspection device;

a core unit that includes a first internal circuit provided corresponding to the first external terminal and a second internal circuit provided corresponding to the second external terminal, and performs signal processing, using at least one of the first internal circuit and the second internal circuit, on the test input signal received by at least one of the first internal circuit and the second internal circuit via the first external terminal to generate a test output signal, the test output signal being output to the external inspection device via the first external terminal;

a switch circuit disposed on a wiring path between the terminal circuit and the core unit, wherein, when the external inspection device is connected to the first external terminal, the switch circuit selectively connects the first external terminal to the first internal circuit, the second internal circuit, or both the first internal circuit and the second internal circuit; and

a switch control circuit that receives a test setting signal from the external inspection device and controls ON and OFF of one or more switches included in the switch circuit based on the test setting signal to select a connection destination of the external inspection device in the switch circuit,

wherein the wafer test process includes outputting, by the probe inspection device, the test setting signal to the switch control circuit to output the test input signal to the first external terminal, or receiving the test output signal from the first external terminal.

11 . The method according to claim 10 , wherein the final test process includes outputting, by the semiconductor inspection device, the test setting signal to the switch control circuit, and outputting a test input signal to the first external terminal, or inputting a test output signal from the first external terminal.

12 . The method according to claim 10 ,

wherein the test setting signal is a serial signal, and

wherein the switch control circuit selects a connection destination of the external inspection device based on a time-series pattern of the serial signal.

13 . The method according to claim 10 ,

wherein the test setting signal is a plurality of voltage signals, and

wherein the switch control circuit selects a connection destination of the external inspection device based on a combination of a plurality of voltage values by the plurality of voltage signals.

14 . The method according to claim 10 , wherein the switch circuit includes:

a first switch that connects the first external terminal and the first internal circuit;

a second switch that connects the second external terminal and the second internal circuit; and

a third switch that connects the first external terminal and the second external terminal.

15 . The method according to claim 14 , wherein the switch circuit fixes the first switch and the second switch to be on and fixing the third switch to be off before shipping the plurality of semiconductor devices after the final test process.