Chip, chip system, and timestamp synchronization method

1 . A chip configured to be in communication connection to another chip, comprising a signal generating circuit, a first signal response circuit and a first delay circuit,

wherein the signal generating circuit is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response circuit and the another chip, so that a second signal response circuit of the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal;

the first delay circuit is configured to perform delay processing on the synchronization request signal transmitted from the signal generating circuit to the first signal response circuit to obtain a delayed synchronization request signal; and

the first signal response circuit is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing an across-chip timestamp synchronization operation,

wherein the first delay circuit is configured to make a time difference between a time when the delayed synchronization request signal is responded to by the first signal response circuit and a time when the synchronization request signal is responded to by the second signal response circuit less than a time difference threshold.

2 . The chip according to claim 1 , wherein the first signal response circuit is further configured to send the first timestamp to the another chip in response to a timestamp acquisition request from the another chip, so that the another chip performs the across-chip timestamp synchronization operation based on the first timestamp and the second timestamp.

3 . The chip according to claim 1 , wherein the first signal response circuit comprises a first signal capture circuit and a first recording circuit,

wherein the first signal capture circuit is configured to receive the delayed synchronization request signal and send a recording command to the first recording circuit in response to the delayed synchronization request signal; and

the first recording circuit is configured to record a current timestamp of the chip as the first timestamp in response to the recording command.

4 . The chip according to claim 1 , wherein the signal generating circuit comprises:

a synchronization signal trigger circuit configured to generate an initial pulse signal; and

a pulse stretch circuit configured to perform a stretching operation on the initial pulse signal to obtain a stretched initial pulse signal, and use the stretched initial pulse signal serving as the synchronization request signal.

5 . The chip according to claim 1 , further comprising:

a first synchronization interface circuit, connected to the signal generating circuit, and configured to transmit the synchronization request signal to a second synchronization interface circuit of the another chip, wherein the first synchronization interface circuit is an exclusive transmission interface for the synchronization request signal.

6 . The chip according to claim 2 , further comprising:

a first data interface circuit connected to the first signal response circuit and configured to send the first timestamp to a second data interface circuit of the another chip; and

a first interconnection bus configured to connect the first signal response circuit and the first data interface circuit.

7 . The chip according to claim 3 , further comprising:

a first timestamp counter configured to continuously count at a fixed frequency, wherein a counted numerical value of the first timestamp counter serves as a timestamp of the chip;

wherein the first recording circuit is configured to capture the numerical value of the first timestamp counter to a register of the first recording circuit in a snapshot manner.

8 . The chip according to claim 1 , further comprising:

a first synchronization control circuit configured to control the signal generating circuit to generate the synchronization request signal; and

a period circuit, configured to record a synchronization period;

wherein the signal generating circuit is further configured to generate the synchronization request signal once every synchronization period to trigger the across-chip timestamp synchronization operation once in a case where a periodic synchronization function is enabled.

9 . A chip configured to be in communication connection to another chip, comprising: a second signal response circuit and a second synchronization control circuit,

wherein the second signal response circuit is configured to record a second timestamp of the chip in response to receiving a synchronization request signal from the another chip, and transmit the synchronization request signal to the second synchronization control circuit; and

the second synchronization control circuit is configured to, in response to receiving the synchronization request signal, acquire the second timestamp from the second signal response circuit, and acquire a first timestamp from the another chip, and execute an across-chip timestamp synchronization operation based on the first timestamp and the second timestamp;

wherein the first timestamp is a timestamp of the another chip recorded by a first signal response circuit of the another chip in response to a delayed synchronization request signal,

wherein a time difference between a time when the delayed synchronization request signal is responded to by the first signal response circuit and a time when the synchronization request signal is responded to by the second signal response circuit is less than a time difference threshold.

10 . The chip according to claim 9 , wherein the second signal response circuit comprises a second signal capture circuit and a second recording circuit,

wherein the second signal capture circuit is configured to receive the synchronization request signal from the another chip, send a recording command to the second recording circuit in response to the synchronization request signal, and transmit the synchronization request signal to the second synchronization control circuit; and

the second recording circuit is configured to record a current timestamp of the chip as the second timestamp in response to the recording command.

11 . The chip according to claim 10 , further comprising:

a second delay circuit, connected between the second signal capture circuit and the second synchronization control circuit, and configured to delay the synchronization request signal transmitted from the second signal capture circuit to the second synchronization control circuit.

12 . The chip according to claim 10 , further comprising:

a second timestamp counter, configured to continuously count at a fixed frequency, wherein a counted numerical value of the second timestamp counter serves as a timestamp of the chip;

wherein the second recording circuit is configured to capture the numerical value of the second timestamp counter to a register of the second recording circuit in a snapshot manner.

13 . The chip according to claim 12 , wherein the second synchronization control circuit is configured to:

in a case where the first timestamp is greater than the second timestamp, compute to obtain an absolute difference value between the first timestamp and the second timestamp as a first absolute difference, and control a numerical value update of the second timestamp counter based on the first absolute difference value; and

in a case where the first timestamp is less than the second timestamp, compute to obtain an absolute difference value between the first timestamp and the second timestamp as a second absolute difference, and control the second timestamp counter to stop counting until a duration of stopping counting reaches a duration corresponding to the second absolute difference value.

14 . The chip according to claim 13 , further comprising:

a first synchronization circuit configured to trigger a numerical value update function in response to the first absolute difference value being written by the second synchronization control circuit to update the numerical value of the second timestamp counter based on the first absolute difference value; and

a second synchronization circuit configured to trigger a stop counting function in response to the second absolute difference value being written by the second synchronization control circuit to make the second timestamp counter stop counting until the duration of stopping counting reaches the duration corresponding to the second absolute difference value.

15 . The chip according to claim 10 , further comprising:

a second synchronization interface circuit, connected to the second signal capture circuit, and configured to receive the synchronization request signal transmitted by the another chip and transmit the synchronization request signal to the second signal capture circuit, wherein the second synchronization interface circuit is an exclusive transmission interface for the synchronization request signal;

a second data interface circuit, connected to the second synchronization control circuit, and configured to receive the first timestamp sent by the another chip and send the first timestamp to the second synchronization control circuit; and

a second interconnection bus, configured to connect the second synchronization control circuit and the second data interface circuit.

16 . A chip system, comprising:

a first chip, which is the chip according to claim 1 ; and

a second chip configured to be in communication connection to the first chip, comprising: a second signal response circuit and a second synchronization control circuit,

wherein the second signal response circuit is configured to record a second timestamp of the chip in response to receiving a synchronization request signal from the first chip, and transmit the synchronization request signal to the second synchronization control circuit; and the second synchronization control circuit is configured to, in response to receiving the synchronization request signal, acquire the second timestamp from the second signal response circuit, and acquire a first timestamp from the first chip, and execute an across-chip timestamp synchronization operation based on the first timestamp and the second timestamp.

17 . A timestamp synchronization method, used for a first chip configured to be in communication connection to a second chip, and the method comprises:

generating a synchronization request signal;

sending the synchronization request signal to the second chip, so that the second chip records a second timestamp of the second chip in response to the synchronization request signal;

performing delay processing on the synchronization request signal to obtain a delayed synchronization request signal; and

recording a first timestamp of the first chip in response to the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for an across-chip timestamp synchronization operation,

wherein the delay processing performed on the synchronization request signal, is configured to make a time difference between a time when the delayed synchronization request signal is responded to by a first signal response circuit of the first chip and a time when the synchronization request signal transmitted to the second chip is responded to by a second signal response circuit of the second chip is less than a time difference threshold.

18 . A timestamp synchronization method, used for a second chip, the second chip is the chip according to claim 10 , the second chip is configured to be in communication connection to a first chip, and the method comprises:

recording a second timestamp of the second chip in response to receiving a synchronization request signal from the first chip;

acquiring a first timestamp from the first chip, wherein the first timestamp is a timestamp of the first chip recorded by the first chip in response to a delayed synchronization request signal; and

executing the across-chip timestamp synchronization operation based on the first timestamp and the second timestamp.