Information processing apparatus and method performed thereby
An information processing apparatus connectable to a UPS, includes motherboards, a first circuit connected to the motherboards to receive first signals therefrom, each first signal indicating whether the corresponding motherboard is operating, a second circuit connected to the motherboards to receive second signals therefrom, each second signal indicating whether power is to be supplied from the UPS to the corresponding motherboard during a power outage, a third circuit for detecting a power outage, and a fourth circuit connected to the first through third circuits. In response to the outage, the fourth circuit supplies power from the UPS to the motherboards when the first and second circuits each receive from at least one motherboard, the first signal indicating that the corresponding motherboard is operating and the second signal indicating that power is to be supplied from the UPS to the corresponding motherboard during a power outage.
1 . An information processing apparatus connectable to an uninterruptible power supply (UPS), comprising:
a plurality of motherboards;
a first circuit connected to the motherboards to receive respective first signals from the motherboards, each of the first signals being of a low level indicating that the corresponding motherboard is not operating or a high level indicating that the corresponding motherboard is operating;
a second circuit connected to the motherboards to receive respective second signals from the motherboards, each of the second signals being of a low level indicating that power is to be supplied from the UPS to the corresponding motherboard during a power outage and a high level indicating that power is not to be supplied from the UPS to the corresponding motherboard during the power outage;
a third circuit configured to output a third signal upon detecting the power outage;
a fourth circuit connected to the first through third circuits and configured to receive power from the UPS;
a fifth circuit directly connected to the first and third circuits; and
a sixth circuit directly connected to the second, fourth, and fifth circuits, wherein
each of the motherboards includes:
a power supply circuit that supplies external power to the corresponding motherboard and that is configured to output the first signal to the first circuit, and
a microcomputer that stores a setting indicating whether power is to be supplied from the UPS to the corresponding motherboard during the power outage and that is configured to output the second signal to the second circuit,
the first circuit is an OR circuit,
the second circuit is an AND circuit,
upon receipt of the third signal from the third circuit, the fifth circuit outputs a fourth signal to the sixth circuit when a signal that is output from the OR circuit is a high level,
upon receipt of the fourth signal from the fifth circuit, the sixth circuit outputs a fifth signal to the fourth circuit when a signal that is output from the AND circuit is a low level, and
in response to receiving the fifth signal from the sixth circuit, the fourth circuit supplies power from the UPS to the motherboards.
2 . The information processing apparatus according to claim 1 , wherein each of the fifth and sixth circuits includes a three-state buffer.
3 . The information processing apparatus according to claim 1 , further comprising:
a base board between the motherboards and the UPS and on which the first through sixth circuits are disposed.
4 . The information processing apparatus according to claim 3 , further comprising:
a first conversion circuit connected to the third circuit on the base board and by which a first direct voltage for operating the base board is generated.
5 . The information processing apparatus according to claim 4 , further comprising:
a second conversion circuit connectable to an external power source, wherein
the second conversion circuit converts an alternating voltage applied by the external power source to a second direct voltage to be applied to the first conversion circuit.
6 . A method performed by an information processing apparatus having an uninterruptible power supply (UPS), the method comprising:
acquiring a plurality of first signals from power supply circuits of a plurality of motherboards, each of the first signals being of a low level indicating that the corresponding motherboard is not operating or a high level indicating that the corresponding motherboard is operating;
acquiring a plurality of second signals from microcomputers of the motherboards, each of the second signals being of a low level indicating that power is to be supplied from the UPS to the corresponding motherboard during a power outage and a high level indicating that power is not to be supplied from the UPS to the corresponding motherboard during the power outage;
detecting the power outage and outputting a third signal;
upon receipt of the third signal, outputting a fourth signal when a signal that is output from an OR circuit to which the plurality of first signals are input, is a high level;
upon receipt of the fourth signal, outputting a fifth signal when a signal that is output from an AND circuit to which the plurality of second signals are input, is a low level; and
upon receipt of the fifth signal, supplying power from the UPS to the motherboards.
7 . An information processing apparatus comprising:
an uninterruptible power supply (UPS);
a plurality of motherboards;
a first circuit connected to the motherboards to receive respective first signals from the motherboards, each of the first signals being of a low level indicating that the corresponding motherboard is not operating or a high level indicating that the corresponding motherboard is operating;
a second circuit connected to the motherboards to receive respective second signals from the motherboards, each of the second signals being of a low level indicating that power is to be supplied from the UPS to the corresponding motherboard during a power outage and a high level indicating that power is not to be supplied from the UPS to the corresponding motherboard during the power outage;
a third circuit configured to output a third signal upon detecting the power outage;
a fourth circuit connected to the first through third circuits and the UPS;
a fifth circuit directly connected to the first and third circuits; and
a sixth circuit directly connected to the second, fourth, and fifth circuits, wherein
each of the motherboards includes:
a power supply circuit that supplies external power to the corresponding motherboard and that is configured to output the first signal to the first circuit, and
a microcomputer that stores a setting indicating whether power is to be supplied from the UPS to the corresponding motherboard during the power outage and that is configured to output the second signal to the second circuit,
the first circuit is an OR circuit,
the second circuit is an AND circuit,
upon receipt of the third signal from the third circuit, the fifth circuit outputs a fourth signal to the sixth circuit when a signal that is output from the OR circuit is a high level,
upon receipt of the fourth signal from the fifth circuit, the sixth circuit outputs a fifth signal to the fourth circuit when a signal that is output from the AND circuit is a low level, and
in response to receiving the fifth signal from the sixth circuit, the fourth circuit supplies power from the UPS to the motherboards.