Memory system capable of patrol read

1 . A memory system comprising:

a semiconductor memory that includes a cell unit having a plurality of memory cells, a column decoder, a row decoder, a voltage generation circuit, and a control circuit connected to the column decoder, the row decoder, and the voltage generation circuit and configured to control the column decoder, the row decoder, and the voltage generation circuit when executing an operation on the plurality of memory cells; and

a memory controller connected to the semiconductor memory via a plurality of data signal lines and a plurality of control signal lines and having a processor and an interface circuit connected to the semiconductor memory via the plurality of data signal lines and the plurality of control signal lines, wherein

the control circuit of the semiconductor memory is configured to:

execute a data read operation on the cell unit using at least first and second read voltages to acquire first data corresponding to the first and second read voltages, respectively, the second read voltage being higher than the first read voltage,

obtain a first number and a second number based on the first data, the first and second numbers indicating a number of the memory cells that are turned on by the data read operation using the first and second read voltages, respectively,

calculate second data having a smaller data size than the first data, using a first average value and a first value, the first average value being an arithmetic mean of the first read voltage and the second read voltage, and the first value being a difference between the first number and the second number, and

transmit the second data to the interface circuit of the memory controller, and

the processor of the memory controller is configured to determine, by comparing the second data that has been transmitted by the semiconductor memory to the interface circuit, with a first threshold value, whether or not to rewrite page data written in the cell unit.

2 . The memory system according to claim 1 , wherein

in the data read operation executed on the cell unit, the control circuit of the semiconductor memory executes reading by further using third and fourth read voltages for the cell unit to acquire the first data further corresponding to the third and fourth read voltages, respectively, the third read voltage being higher than the second read voltage, the fourth read voltage being higher than the third read voltage, and the first data further including a third number and a fourth number, the third and fourth numbers indicating the number of memory cells that are turned on by the data read operation using the third and fourth read voltages, respectively,

the control circuit of the semiconductor memory is configured to compute first, second, and third difference points, respectively, based on the first, second, third, and fourth read voltages and the first, second, third, and fourth numbers of memory cells,

the first difference point is represented by the first average value and the first value which is a difference between the second number of memory cells and the first number of memory cells,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second value which is a difference between the third number of memory cells and the second number of memory cells,

the third difference point is represented by a third average value which is an arithmetic mean of the third read voltage and the fourth read voltage, and a third value which is a difference between the fourth number of memory cells and the third number of memory cells, and

the control circuit of the semiconductor memory is configured to calculate the second data using a minimum value of an approximate curve passing through the first difference point, the second difference point, and the third difference point.

3 . The memory system according to claim 2 , wherein

the approximate curve is represented by a quadratic function.

4 . The memory system according to claim 1 , wherein

in the data read operation executed on the cell unit, the control circuit of the semiconductor memory executes reading by further using a third read voltage for the cell unit to acquire the first data further corresponding to the third read voltage, the third read voltage being higher than the second read voltage, and the first data further including a third number indicating the number of memory cells that are turned on by the data read operation using the third read voltage,

the control circuit of the semiconductor memory is configured to acquire first and second difference points, respectively, based on the first, second, and third read voltages and the first, second, and third numbers of memory cells,

the first difference point is represented by the first average value and the first value,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second value which is a difference between the third number of memory cells and the second number of memory cells, and

when a threshold voltage of each of the plurality of memory cells is represented on a horizontal axis and the number of memory cells is represented on a vertical axis, the control circuit of the semiconductor memory calculates an intersection of a first diagonal line connecting the second difference point and a first threshold voltage corresponding to the first average value, and a second diagonal line connecting the first difference point and a second threshold voltage corresponding to the second average value, and sets the number of memory cells corresponding to the intersection as the second data.

5 . The memory system according to claim 1 , wherein

the memory controller executes rewriting of the page data written in the cell unit when the second data is higher than a first threshold, and does not execute the rewriting of the page data written in the cell unit when the second data is equal to or smaller than the first threshold.

6 . The memory system according to claim 1 , wherein

each of the plurality of memory cells stores data of different values corresponding to a plurality of threshold voltages, and each of the one or more read voltages is a voltage for determining a value of data stored in a memory cell.

7 . The memory system according to claim 1 , wherein

the semiconductor memory further includes a word line, and the plurality of memory cells provided in the cell unit are connected to the word line.

8 . The memory system according to claim 1 , wherein

the second data is an estimate of the number of error bits in the page data obtained by the data read operation executed on the cell unit.

9 . A memory system comprising:

a first memory that includes:

a plurality of cell units including a first cell unit, and

a control circuit for controlling the plurality of cell units, the control circuit configured to use a first read voltage as a read voltage at a first time for a plurality of memory cells in the first cell unit;

a second memory; and

a controller configured to:

obtain a second read voltage as a result of a tracking operation executed on the plurality of memory cells at a second time after the first time,

calculate a voltage difference between the first read voltage and the obtained second read voltage,

store the voltage difference in the second memory,

read the voltage difference from the second memory at a third time,

calculate first data based on the voltage difference read from the second memory and without reliance on results of reading data from the first memory after the second time, and

determine whether or not to rewrite page data written in the cell unit based on the first data, wherein

the controller is further configured to determine to rewrite the page data written in the first cell unit in response to the first data being equal to or larger than a first threshold.

10 . The memory system according to claim 9 , wherein

each of the plurality of memory cells stores data of different values corresponding to a plurality of threshold voltages, and the first operation is an operation for detecting a voltage for determining a value of data stored in a memory cell.

11 . The memory system according to claim 9 , wherein

the first data is an estimate of the number of error bits in the page data obtained by a data read operation executed on the first cell unit.

12 . The memory system according to claim 1 , wherein

the processor of the memory controller is configured to determine whether or not an additional data read operation is to be executed on the cell unit by comparing the second data with the first threshold value,

in response to an instruction from the memory controller to execute the additional data read operation on the cell unit, the control circuit of the semiconductor memory executes the additional data read operation for the cell unit, acquires third data by the additional data read operation, and transmits the third data to the memory controller, and

the processor of the memory controller is configured to determine whether or not to rewrite the page data written in the cell unit based on the third data.

13 . The memory system according to claim 12 , wherein

the second data is an estimate of the number of error bits in the page data obtained by the first data read operation executed on the cell unit.

14 . The memory system according to claim 12 , wherein

in the first data read operation executed on the cell unit, the control circuit of the semiconductor memory executes reading by further using third and fourth read voltages for the cell unit to acquire the first data further corresponding to the third and fourth read voltages, respectively, the third read voltage being higher than the second read voltage, the fourth read voltage being higher than the third read voltage, and the first data further including a third number and a fourth number, the third and fourth numbers indicating the number of memory cells that are turned on by the first data read operation using the third and fourth read voltages, respectively,

the control circuit of the semiconductor memory computes first, second, and third difference points, respectively, based on the first, second, third, and fourth read voltages and the first, second, third, and fourth numbers of memory cells,

the first difference point is represented by the first average value and the first value,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second value which is a difference between the third number of memory cells and the second number of memory cells,

the third difference point is represented by a third average value which is an arithmetic mean of the third read voltage and the fourth read voltage, and a third value which is a difference between the fourth number of memory cells and the third number of memory cells, and

the control circuit of the semiconductor memory is configured to calculate the second data using a minimum value of an approximate curve passing through the first difference point, the second difference point, and the third difference point.

15 . The memory system according to claim 12 , wherein

in the first data read operation executed on the cell unit, the control circuit of the semiconductor memory executes reading by further using a third read voltage for the cell unit to acquire the first data further corresponding to the third read voltage, the third read voltage being higher than the second read voltage, and the first data further including a third number indicating the number of memory cells that are turned on by the first data read operation using the third read voltage,

the control circuit of the semiconductor memory is configured to acquire first and second difference points, respectively, based on the first, second, and third read voltages and the first, second, and third number of memory cells,

the first difference point is represented by the first average value, and the first value,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second value which is a difference between the third number of memory cells and the second number of memory cells, and

when a threshold voltage of each of the plurality of memory cells is represented on a horizontal axis and the number of memory cells is represented on a vertical axis, the control circuit of the semiconductor memory calculates an intersection of a first diagonal line connecting the second difference point and a first threshold voltage corresponding to the first average value, and a second diagonal line connecting the first difference point and a second threshold voltage corresponding to the second average value, and sets the number of memory cells corresponding to the intersection as the second data.

16 . The memory system according to claim 9 , wherein

in the tracking operation, the controller obtains a voltage corresponding to a valley position of threshold voltage distributions of the plurality of memory cells as the second read voltage.

17 . A memory system comprising:

a plurality of semiconductor memory chips, each of the plurality of semiconductor memory chips including a cell unit having a plurality of memory cells and a corresponding control circuit for controlling the plurality of memory cells; and

a controller connected to the plurality of semiconductor memory chips via a plurality of data signal lines and a plurality of control signal lines, wherein

the corresponding control circuit for each of the plurality of semiconductor memory chips is configured to:

execute a data read operation on the cell unit included in the corresponding one of the plurality of semiconductor memory chips using one or more read voltages,

acquire first data by the data read operation,

generate second data having a smaller data size than the first data, based on the first data, and

transmit the second data to the controller, and

the controller is configured to determine, based on the second data received from one of the plurality of semiconductor memory chips, whether or not to rewrite page data written in the cell unit included in the corresponding one of the plurality of semiconductor memory chips.

18 . The memory system according to claim 17 , wherein

each of the plurality of control circuits is included in the corresponding one of the plurality of semiconductor memory chips.

19 . The memory system according to claim 17 , wherein

each of the plurality of semiconductor memory chips further includes a logic control circuit configured to receive a command latch enable signal from the controller, and

the number of the control circuits included in the memory system is equal to the number of the logic control circuits included in the memory system.

20 . The memory system according to claim 17 , wherein

each of the plurality of control circuits is configured to execute the data read operation by using first, second, third, and fourth read voltages for the cell unit included in the corresponding one of the plurality of semiconductor memory chips to acquire the first data corresponding to the first, second, third, and fourth read voltages, respectively, the second read voltage being higher than the first read voltage, the third read voltage being higher than the second read voltage, the fourth read voltage being higher than the third read voltage, and the first data including a first number, a second number, a third number, and a fourth number, the first, second, third, and fourth numbers indicating the number of memory cells that are turned on by the data read operation using the first, second, third, and fourth read voltages, respectively,

each of the plurality of control circuits is configured to compute first, second, and third difference points, respectively, based on the first, second, third, and fourth read voltages and the first, second, third, and fourth numbers of memory cells,

the first difference point is represented by a first average value which is an arithmetic mean of the first read voltage and the second read voltage, and a first value which is a difference between the second number of memory cells and the first number of memory cells,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second value which is a difference between the third number of memory cells and the second number of memory cells,

the third difference point is represented by a third average value which is an arithmetic mean of the third read voltage and the fourth read voltage, and a third value which is a difference between the fourth number of memory cells and the third number of memory cells, and

each of the plurality of control circuits is configured to calculate the second data using a minimum value of an approximate curve passing through the first difference point, the second difference point, and the third difference point.

21 . The memory system according to claim 17 , wherein

each of the plurality of control circuits is configured to execute the data read operation by using first, second, and third read voltages for the cell unit included in the corresponding one of the plurality of semiconductor memory chips to acquire the first data corresponding to the first, second, and third read voltages, respectively, the second read voltage being higher than the first read voltage, the third read voltage being higher than the second read voltage, and the first data including a first number, a second number, and a third number, the first, second, and third numbers indicating the number of memory cells that are turned on by the data read operation using the first, second, and third read voltages, respectively,

each of the plurality of control circuits is configured to compute first and second difference points, respectively, based on the first, second, and third read voltages and the first, second, and third numbers of memory cells,

the first difference point is represented by a first average value which is an arithmetic mean of the first read voltage and the second read voltage, and a first difference value which is a difference between the second number of memory cells and the first number of memory cells,

the second difference point is represented by a second average value which is an arithmetic mean of the second read voltage and the third read voltage, and a second difference value which is a difference between the third number of memory cells and the second number of memory cells, and

when a threshold voltage of each of the plurality of memory cells included in the corresponding one of the plurality of semiconductor memory chips is represented on a horizontal axis and the number of memory cells is represented on a vertical axis, the control circuit calculates an intersection of a first diagonal line connecting the second difference point and a first threshold voltage corresponding to the first average value, and a second diagonal line connecting the first difference point and a second threshold voltage corresponding to the second average value, and sets the number of memory cells corresponding to the intersection as the second data.