Nonvolatile memory

1 . A nonvolatile memory device comprising:

a memory block including a plurality of cell strings, each cell string of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit-lines and a common source line;

a page buffer circuit connected to the plurality of cell strings through the plurality of bit-lines; and

a control circuit configured to control a read operation by:

latching a first sensing data and a second sensing data in the page buffer circuit by performing a first read operation on a selected word-line designated by an access address, among a plurality of word-lines of the memory block, based on a read voltage set;

latching a third sensing data in the page buffer circuit by performing a second read operation on an aggressor word-line adjacent to the selected word-line, based on at least one adjacent read voltage;

selecting the first sensing data or the second sensing data as a hard decision data based on a program state of the third sensing data; and

generating a soft decision data by using the first sensing data and the second sensing data.

2 . The nonvolatile memory device of claim 1 , wherein the control circuit is configured to control the page buffer circuit to generate the soft decision data by performing an exclusive NOR operation on the first sensing data and the second sensing data.

3 . The nonvolatile memory device of claim 1 , wherein the control circuit is configured to control the page buffer circuit to generate the soft decision data by performing an exclusive OR operation on the first sensing data and the second sensing data.

4 . The nonvolatile memory device of claim 1 , wherein, when a threshold voltage distribution of the program state of the third sensing data of each of non-aggressor cells of memory cells coupled to the aggressor word-line is smaller than the at least one adjacent read voltage, the control circuit is configured to select the first sensing data of each of first memory cells corresponding to the non-aggressor cells, among memory cells coupled to the selected word-line, as the hard decision data.

5 . The nonvolatile memory device of claim 1 , wherein, when a threshold voltage distribution of the program state of the third sensing data of each of aggressor cells of memory cells coupled to the aggressor word-line is equal to or greater than the at least one adjacent read voltage, the control circuit is configured to select the second sensing data of each of second memory cells corresponding to the aggressor cells, among memory cells coupled to the selected word-line, as the hard decision data.

6 . The nonvolatile memory device of claim 1 , wherein the page buffer circuit includes:

a plurality of page buffers, wherein each of the plurality of page buffers is connected to a respective cell string of the plurality of cell strings through a respective bit-line of the plurality of bit-lines; and

a data cooker connected to the plurality of page buffers, wherein the data cooker is configured to generate the soft decision data by using the first sensing data and the second sensing data.

7 . The nonvolatile memory device of claim 6 , wherein the control circuit is configured to control the page buffer circuit to:

store the first sensing data in a first latch of a respective page buffer of the plurality of page buffers;

store the second sensing data in a second latch of a respective page buffer of the plurality of page buffers; and

store the third sensing data in a third latch of a respective page buffer of the plurality of page buffers.

8 . The nonvolatile memory device of claim 1 , wherein the page buffer circuit includes:

a plurality of page buffers, wherein each of the plurality of page buffers is connected to a respective cell string of the plurality of cell strings through a respective bit-line of the plurality of bit-lines; and

a data cooker connected to the plurality of page buffers, wherein the data cooker is configured to generate the soft decision data by using the first sensing data and the second sensing data,

wherein the control circuit is configured to control the page buffer circuit to:

store three or more sensing data in first latches of a respective page buffer of the plurality of page buffers by applying the read voltage set including three or more data recovery read voltages to the selected word-line; and

store two or more decision data in second latches of a respective page buffer of the plurality of page buffers by applying the at least one adjacent read voltage including two or more adjacent read voltages to the aggressor word-line, and

wherein the control circuit is configured to select one of three or more sensing data as the hard decision data based on the two or more decision data and generate the soft decision data by using the three or more sensing data.

9 . The nonvolatile memory device of claim 1 , wherein the control circuit is configured to control the page buffer circuit to:

output the soft decision data after outputting the hard decision data; or

output the hard decision data after outputting the soft decision data.

10 . The nonvolatile memory device of claim 1 , wherein the control circuit includes an aggressor word-line selector configured to select the aggressor word-line based on a row address included in the access address,

wherein the plurality of word-lines are programmed from the plurality of bit-lines to the common source line,

wherein the plurality of word-lines include:

a first word-line;

a second word-line on the first word-line in a direction perpendicular to a substrate and adjacent to the first word-line; and

a third word-line on the second word-line in the direction perpendicular to the substrate and adjacent to the second word-line, and

wherein the second word-line is the selected word-line.

11 . The nonvolatile memory device of claim 10 , wherein, when the first word-line is a normal word-line, the aggressor word-line selector is configured to select the first word-line as the aggressor word-line.

12 . The nonvolatile memory device of claim 10 , wherein, when the first word-line is a dummy word-line, the aggressor word-line selector is configured to select the third word-line as the aggressor word-line,

wherein the memory block is implemented in a multi-stack structure including two or more stacks, and the dummy word-line is placed at a boundary of the stacks.

13 . The nonvolatile memory device of claim 10 , wherein, when the first word-line is a word-line on which programming is not performed, the aggressor word-line selector is configured to select the third word-line as the aggressor word-line.

14 . A memory system comprising a nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device comprises:

a memory block including a plurality of cell strings, each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit-lines and a common source line;

a page buffer circuit connected to the plurality of cell strings through the plurality of bit-lines; and

a control circuit configured to control a read operation by:

latching a first sensing data and a second sensing data in the page buffer circuit by performing a first read operation on a selected word-line designated by an access address, among a plurality of word-lines of the memory block, based on a read voltage set;

latching a third sensing data in the page buffer circuit by performing a second read operation on an aggressor word-line adjacent to the selected word-line, based on at least one group read voltage;

selecting the first sensing data or the second sensing data as a hard decision data based on a program state of the third sensing data; and

providing the hard decision data to the memory controller.

15 . The memory system of claim 14 , wherein:

the memory controller includes an error correction code (ECC) decoder configured to perform a first ECC decoding on the hard decision data,

the memory controller is configured to transmit a request of a soft decision data to the nonvolatile memory device when the first ECC decoding fails,

the control circuit is further configured to control the read operation by providing the soft decision data to the memory controller in response to the request, and

the ECC decoder is configured to perform a second ECC decoding on the soft decision data provided from the nonvolatile memory device.

16 . The memory system of claim 14 ,

wherein the control circuit is further configured to control the read operation by

generating a soft decision data by using the first sensing data and the second sensing data; and

providing the soft decision data to the memory controller; and

wherein the memory controller includes error correction code (ECC) decoder configured to:

perform a first ECC decoding on the hard decision data; and

perform a second ECC decoding on the soft decision data when the first ECC decoding fails.

17 . The memory system of claim 14 ,

wherein the control circuit is further configured to control the read operation by providing the first sensing data and the second sensing data to the memory controller,

wherein the memory controller is configured to generate a soft decision data by using the first sensing data and the second sensing data, and

wherein the memory controller includes error correction code (ECC) decoder configured to:

perform a first ECC decoding on the hard decision data; and

perform a second ECC decoding on the soft decision data when the first ECC decoding fails.

18 . A method of controlling an operation of a nonvolatile memory device comprising a memory block including a plurality of cell strings, each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit-lines and a common source line, the method comprising:

latching a first sensing data and a second sensing data in a page buffer circuit by performing a first read operation on a selected word-line designated by an access address, from among a plurality of word-lines of the memory block, based on a read voltage set;

latching a third sensing data in the page buffer circuit by performing a second read operation on an aggressor word-line adjacent to the selected word-line, based on at least one group read voltage;

selecting the first sensing data or the second sensing data as a hard decision data based on a program state of the third sensing data; and

generating a soft decision data by using the first sensing data and the second sensing data.

19 . The method of claim 18 , wherein generating the soft decision data includes performing one of an exclusive NOR operation and an exclusive OR operation on the first sensing data and the second sensing data.

20 . The method of claim 18 , further comprising selecting one of at least two word-lines adjacent to the selected word-line as the aggressor word-line based on a row address included in the selected word-line designated by the access address and programming progress information before performing the second read operation.