Fabric memory network-on-chip extension to ALM registers and LUTRAM
Systems or methods of the present disclosure may provide a programmable fabric including programmable logic. The programmable logic may include memory, a network-on-chip (NOC), and at least one micro NOC formed with hardened resources in the programmable fabric. Further, the at least one micro NOC may be communicatively coupled to the NOC and to the programmable logic. Additionally, the at least one micro NOC may selectively route data between the NOC and the programmable logic.
1 . An integrated circuit device, comprising:
a programmable fabric comprising programmable logic, wherein the programmable logic comprises memory;
a network-on-chip (NOC); and
at least one micro NOC formed with hardened resources in the programmable fabric, wherein:
the at least one micro NOC is communicatively coupled to the NOC and to the programmable logic; and
the at least one micro NOC is configurable to selectively route data between the NOC and the programmable logic.
2 . The integrated circuit device of claim 1 , wherein the memory comprises lookup table random-access memory (LUTRAM), a register, or both.
3 . The integrated circuit device of claim 2 , wherein:
the programmable logic comprises a programmable logic element; and
the memory is included in the programmable logic element.
4 . The integrated circuit device of claim 2 , wherein the memory comprises the LUTRAM.
5 . The integrated circuit device of claim 2 , wherein the memory comprises the register.
6 . The integrated circuit device of claim 1 , wherein the at least one micro NOC is configurable to selectively route the data to the memory via the programmable logic.
7 . The integrated circuit device of claim 1 , comprising a controller configurable to cause the data to be routed from the at least one micro NOC to the memory.
8 . The integrated circuit device of claim 7 , wherein the controller is configurable to cause the integrated circuit device to:
operate in a first mode of operation in which data is read from or written to the memory; and
operate in a second mode of operation in which the programmable logic processes data based on values stored in the memory.
9 . The integrated circuit device of claim 8 , comprising clock selection circuitry configurable to cause the memory to operate, based on whether the integrated circuit device is configured to operate in the first mode of operation or the second mode of operation, using a first clock rate or a second clock rate that is different than the first clock rate.
10 . The integrated circuit device of claim 8 , wherein the memory comprises an address counter configurable to track one or more addresses in the memory to which data is written or from which data is read.
11 . The integrated circuit device of claim 1 , wherein the programmable logic is configurable to perform double data rate (DDR), quadruple data rate (QDR), or DDR and QDR data transfers.
12 . The integrated circuit device of claim 1 , wherein the integrated circuit device comprises a field-programmable gate array.
13 . A programmable logic device, comprising:
a programmable fabric comprising programmable logic, wherein the programmable logic comprises memory;
a network-on-chip (NOC); and
at least one micro NOC formed with hardened resources in the programmable fabric, wherein:
the at least one micro NOC is communicatively coupled to the NOC and to the programmable logic; and
the at least one micro NOC is configurable to selectively route data between the NOC and the memory.
14 . The programmable logic device of claim 13 , wherein the memory comprises lookup table random-access memory (LUTRAM), a register of a programmable logic element, or both.
15 . The programmable logic device of claim 13 , wherein the memory is included within an adaptive logic module formed in the programmable fabric.
16 . The programmable logic device of claim 13 , wherein the programmable logic device comprises a field-programmable gate array.
17 . A system comprising:
a substrate;
a first die mounted on the substrate; and
a second die mounted on the substrate, comprising:
a programmable fabric comprising programmable logic, wherein the programmable logic comprises memory;
a network-on-chip (NOC); and
at least one micro NOC formed with hardened resources in the programmable fabric, wherein:
the at least one micro NOC is communicatively coupled to the NOC and to the programmable logic; and
the at least one micro NOC is configurable to selectively route data between the NOC and the programmable logic.
18 . The system of claim 17 , wherein the first die is an integrated circuit die.
19 . The system of claim 17 , wherein the first die comprises a memory die or a storage die.
20 . The system of claim 17 , wherein the system is implemented as a multi-die package.