Memory systems, memory controllers, control methods, and storage mediums to increase utilization of resources by multiple commands

1 . A memory system, comprising:

a memory device including a memory chip; and

a memory controller coupled to the memory device and configured to:

send a first command phase of a first command, wherein the first command includes the first command phase and a second command phase with an idle time provided between the first command phase and the second command phase, and wherein the first command phase and the second command phase are consecutive command phases;

send a second command in the idle time of the first command, wherein, in the idle time of the first command, the first command phase has terminated and the second command phase has not begun; and

send the second command phase of the first command when the idle time of the first command expires.

2 . The memory system of claim 1 , wherein a command occupancy time corresponding to the second command is less than the idle time of the first command.

3 . The memory system of claim 1 , wherein the memory controller is further configured to:

acquire the first command;

determine whether a command occupancy time of the first command is less than a first time threshold, wherein the first time threshold is less than or equal to the idle time of the first command; and

determine that the first command is the second command, in response to the command occupancy time of the first command being less than the first time threshold.

4 . The memory system of claim 1 , wherein the second command is a status read command.

5 . The memory system of claim 1 , wherein the memory controller is further configured to send a third command in the idle time of the first command, wherein a sum of a command occupancy time corresponding to the second command and a command occupancy time corresponding to the third command is less than the idle time of the first command.

6 . The memory system of claim 1 , wherein the memory controller is further configured to:

start timing upon completion of sending the first command phase of the first command;

send the second command during the timing; and

send the second command phase of the first command when the timing reaches the idle time of the first command.

7 . The memory system of claim 1 , wherein the memory controller is further configured to:

acquire the second command;

determine whether an idle time of the second command is greater than a second time threshold; and

determine that the second command is the first command, in response to the idle time of the second command being greater than the second time threshold.

8 . The memory system of claim 1 , wherein the idle time of the first command includes a change column setup time of the first command.

9 . The memory system of claim 1 , wherein the first command corresponds to a first enable, and the second command corresponds to a second enable.

10 . The memory system of claim 9 , wherein the first enable and the second enable respectively correspond to memory chips located on a same physical channel.

11 . A control method of a memory system, comprising:

sending a first command phase of a first command, wherein the first command includes the first command phase and a second command phase with an idle time provided between the first command phase and the second command phase, and wherein the first command phase and the second command phase are consecutive command phases;

sending a second command in the idle time of the first command, wherein, in the idle time of the first command, the first command phase has terminated and the second command phase has not begun; and

sending the second command phase of the first command when the idle time of the first command expires.

12 . The control method of claim 11 , wherein a command occupancy time corresponding to the second command is less than the idle time of the first command.

13 . The control method of claim 12 , further including:

acquiring the first command;

determining whether a command occupancy time of the first command is less than a first time threshold, wherein the first time threshold is less than or equal to the idle time of the first command; and

determining that the first command is the second command, in response to the command occupancy time of the first command being less than the first time threshold.

14 . The control method of claim 11 , wherein the second command is a status read command.

15 . The control method of claim 11 , further including sending a third command in the idle time of the first command, wherein a sum of a command occupancy time corresponding to the second command and a command occupancy time corresponding to the third command is less than the idle time of the first command.

16 . The control method of claim 11 , wherein the sending the second command in the idle time of the first command includes:

starting timing upon completion of sending the first command phase of the first command;

sending the second command during the timing; and

sending the second command phase of the first command when the timing reaches the idle time of the first command.

17 . The control method of claim 11 , further including:

acquiring the second command;

determining whether an idle time of the second command is greater than a second time threshold; and

determining that the second command is the first command, in response to the idle time of the second command being greater than the second time threshold.

18 . The control method of claim 11 , wherein the idle time of the first command includes a change column setup time of the first command.

19 . The control method of claim 11 , wherein the first command corresponds to a first enable, the second command corresponds to a second enable.

20 . A non-transitory computer readable storage medium, wherein control instructions in the non-transitory computer readable storage medium, when executed by at least one processor, enable the at least one processor to perform a control method of a memory system, the control method comprising:

sending a first command phase of a first command, wherein the first command includes the first command phase and a second command phase with an idle time provided between the first command phase and the second command phase, and wherein the first command phase and the second command phase are consecutive command phases;

sending a second command in the idle time of the first command, wherein, in the idle time of the first command, the first command phase has terminated and the second command phase has not begun; and

sending the second command phase of the first command when the idle time of the first command expires.