Memory systems, operating methods for memory systems, controller and storage medium
The present application provides a memory system, a method for operating the memory system, a controller and a storage medium. The memory system includes: a memory device and a controller; the controller is configured to send a read command to the memory device; the memory device is configured to read data stored in a first memory cell in the memory device according to the read command; the first memory cell and the second memory cell are located in the same memory string; the second memory cell is a memory cell that has not yet been written with data; the controller is further configured to send a write command to the memory device; the memory device is further configured to write data read from the first memory cell to the second memory cell according to the write command.
1 . A memory system, comprising:
a controller configured to: send a read command to a memory device; and
the memory device configured to: read data stored in a first memory cell in the memory device according to the read command; wherein the first memory cell and a second memory cell are located in a same memory string, and word lines coupled to the first memory cell and the second memory cell respectively are adjacent, the second memory cell is a memory cell that has not yet been written with data;
the controller is further configured to send a write command to the memory device; and
the memory device is further configured to write data read from the first memory cell to the second memory cell according to the write command.
2 . The memory system of claim 1 , wherein
the controller is further configured to obtain a physical address of the first memory cell and a physical address of the second memory cell; and
the controller is configured to send the read command to the memory device according to the physical address of the first memory cell, and send the write command to the memory device according to the physical address of the second memory cell.
3 . The memory system of claim 1 , wherein the controller is further configured to:
before sending the read command to the memory device, in response to a memory block being open and data in a third memory cell in the memory block being valid data, determine the first memory cell in the memory block and the second memory cell corresponding to the first memory cell according to a location of the third memory cell in the memory block,
wherein, the third memory cell is a last memory cell among the memory cells in the memory block that have been written with data.
4 . The memory system of claim 3 , wherein the controller is configured to:
in response to the third memory cell being the last memory cell in a n-th word line of the memory block,
determine memory cells in the n-th word line respectively as the first memory cells, and determine a memory cell in the same memory string as the first memory cell in the (n+1)-th word line of the memory block as the second memory cell corresponding to the first memory cell; and
wherein, 1≤n<N, n is an integer, and M is the number of word lines in the memory block.
5 . The memory system of claim 3 , wherein the controller is configured to:
in response to the third memory cell not being the last memory cell in the n-th word line of the memory block,
determine a non-empty memory cell in the n-th word line as the first memory cell, and determine a memory cell in the same memory string as the first memory cell in the (n+1)-th word line of the memory block as the second memory cell corresponding to the first memory cell; and
determine the memory cell in the n-th word line that has not yet been written with data as the second memory cell, and determine a memory cell in the same memory string as the second memory cell in a (n−1)-th word line of the memory block as the first memory cell corresponding to the second memory cell,
wherein, 1≤n<N, n is an integer, and M is the number of word lines in the memory block.
6 . The memory system of claim 3 , wherein the controller is further configured to:
before determining the first memory cell and the second memory cell in the memory block according to the location of the third memory cell in the memory block, check whether the third memory cell in the memory block is set with a filling flag, wherein the filling flag is to indicate that data in a corresponding memory cell is invalid filled data; and
in response to the third memory cell not being set with a filling flag, determine that data in the third memory cell is valid data.
7 . The memory system of claim 6 , wherein the controller is further configured to:
after the memory device successfully writes the data read from the first memory cell into the second memory cell, set the filling flag for the second memory cell.
8 . The memory system of claim 7 , wherein the controller is configured to:
in a logical address to physical address mapping table, set the filling flag corresponding to the physical address of the second memory cell; or
outside the logical address to physical address mapping table, set the filling flag corresponding to identification information of the second memory cell.
9 . The memory system of claim 7 , wherein the controller is further configured to:
when the memory block is erased, unset a filling flag corresponding to a memory cell in the memory block.
10 . The memory system of claim 1 , wherein the controller is configured to:
in the case that a time duration in which data has been written in the first memory cell reaches a time duration threshold, send the read command to the memory device.
11 . A method for operating a memory system, comprising:
sending, by a controller, a read command to a memory device;
reading, by the memory device, data stored in a first memory cell in the memory device according to the read command; wherein the first memory cell and a second memory cell are located in a same memory string, and word lines coupled to the first memory cell and the second memory cell respectively are adjacent, and the second memory cell is a memory cell that has not yet been written with data;
sending, by the controller, a write command to the memory device; and
writing, by the memory device, data read from the first memory cell to the second memory cell according to the write command.
12 . The method of claim 11 , wherein before sending, by the controller, a read command to a memory device, the method further comprises:
obtaining, by the controller, a physical address of the first memory cell and a physical address of the second memory cell;
the sending, by the controller, a write command to the memory device comprising:
sending, by the controller, the read command to the memory device according to the physical address of the first memory cell; and
the sending, by the controller, a write command to the memory device comprising:
sending, by the controller, the write command to the memory device according to the physical address of the second memory cell.
13 . The method of claim 11 , wherein before sending, by the controller, the read command to the memory device, the method further comprises:
in the case that the memory block is open and data in a third memory cell in the memory block is valid data,
determining, by the controller, the first memory cell in the memory block and the second memory cell corresponding to the first memory cell according to a location of the third memory cell in the memory block; and
wherein, the third memory cell is a last memory cell among the memory cells in the memory block that have been written with data.
14 . The method of claim 13 , wherein, the determining, by the controller, the first memory cell in the memory block and the second memory cell corresponding to the first memory cell according to the location of the third memory cell in the memory block comprises:
in the case that the third memory cell is a last memory cell in the n-th word line of the memory block,
by the controller, determining memory cells in the n-th word line respectively as the first memory cells, and determining a memory cell in the same memory string as the first memory cell in the (n+1)-th word line of the memory block as the second memory cell corresponding to the first memory cell; and
wherein, 1≤n<N, n is an integer, and M is the number of word lines in the memory block.
15 . The method of claim 13 , wherein, the determining, by the controller, the first memory cell in the memory block and the second memory cell corresponding to the first memory cell according to the location of the third memory cell in the memory block comprises:
in the case that the third memory cell is not the last memory cell in the n-th word line of the memory block,
by the controller, determining a non-empty memory cell in the n-th word line as the first memory cell, and determining a memory cell in the same memory string as the first memory cell in the (n+1)-th word line of the memory block as the second memory cell corresponding to the first memory cell; and
by the controller, determining a memory cell in the n-th word line that has not yet been written with data as the second memory cell, and determining a memory cell in the same memory string as the second memory cell in the (n−1)-th word line of the memory block as the first memory cell corresponding to the second memory cell,
wherein, 1≤n<N, n is an integer, and M is the number of word lines in the memory block.
16 . The method of claim 13 , further comprises:
before determining the first memory cell and the second memory cell in the memory block according to the location of the third memory cell in the memory block, by the controller, checking whether the third memory cell in the memory block is set with a filling flag, wherein the filling flag is to indicate that the data in a corresponding memory cell is invalid filled data; and
in the case that the third memory cell is not set with a filling flag, determining that data in the third memory cell is valid data.
17 . The method of claim 16 , further comprises:
after the memory device successfully writes the data read from the first memory cell into the second memory cell, setting, by the controller, the filling flag for the second memory cell.
18 . The method of claim 17 , wherein the setting, by the controller, the filling flag for the second memory cell comprises:
in a logical address to physical address mapping table, setting, by the controller, the filling flag corresponding to the physical address of the second memory cell; or
outside the logical address to physical address mapping table, setting, by the controller, the filling flag corresponding to identification information of the second memory cell.
19 . The method of claim 17 , further comprises:
when the memory block is erased, unsetting, by the controller, a filling flag corresponding to a memory cell in the memory block.
20 . A controller, comprising:
a cache; and
a control circuit configured to:
send a read command to a memory device; wherein the read command is for instructing the memory device to read data stored in a first memory cell in the memory device, and the first memory cell and a second memory cell are located in a same memory string, and word lines coupled to the first memory cell and the second memory cell respectively are adjacent, the second memory cell is a memory cell that has not yet been written with data; and
send a write command to the memory device; wherein the write command is for instructing the memory device to write the data read from the first memory cell to the second memory cell.