Hybrid compute-in-memory
A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.
1 . An apparatus, comprising:
a capacitor including a first plate and a second plate;
a voltage source;
a first switch configured to close responsive to a first activation bit signal;
a second switch coupled in series with the first switch between the voltage source and the first plate, the second switch being configured to close responsive to a first filter weight bit signal to multiply the first filter weight signal bit with the first activation bit signal to charge the first plate;
a third switch configured to close responsive to a second activation bit signal; and
a fourth switch coupled in series with the third switch between the voltage source and the second plate, the fourth switch being configured to close responsive to a second filter weight bit signal to multiply the second filter weight bit signal with the second activation bit signal to charge the second plate; and
wherein a voltage of the first plate is a tri-level voltage prior to accumulation as a multiple of a charged voltage of an arithmetic cell from a plurality of arithmetic cells and wherein the first plate is coupled to an analog-to-digital converter (ADC) to digitize a sum of multiplications from the plurality of arithmetic cells.
2 . The apparatus of claim 1 , further comprising:
a first multiplexer configured to select between a first pair of activation bit signals to provide the first activation bit signal.
3 . The apparatus of claim 2 , further comprising:
a second multiplexer configured to select between a second pair of activation bit signals to provide the second activation bit signal.
4 . The apparatus of claim 1 , further comprising:
a fifth switch coupled between the first plate and ground, wherein the fifth switch is configured to close responsive to a first reset signal.
5 . The apparatus of claim 4 , further comprising:
a sixth switch coupled between the second plate and ground, wherein the sixth switch is configured to close responsive to a second reset signal.
6 . The apparatus of claim 1 , further comprising:
a fifth switch; and
the analog-to-digital converter having an input terminal coupled to the first plate through the fifth switch.
7 . The apparatus of claim 6 , further comprising:
a digital adder coupled to an output terminal of the analog-to-digital converter.
8 . The apparatus of claim 1 , further comprising:
a fifth switch coupled between the second plate and ground, the fifth switch being configured to close responsive to a complement of the second filter weight bit signal.
9 . The apparatus of claim 1 , wherein the voltage source is a node for a power supply voltage for the compute-in-memory.
10 . The apparatus of claim 1 , wherein the voltage source is configured to provide a reference voltage that is a fraction of a power supply voltage for the compute-in-memory.
11 . The apparatus of claim 10 , wherein the fraction of the power supply voltage is approximately one-half of the power supply voltage.
12 . The apparatus of claim 1 , wherein the voltage source is configured to provide a first reference voltage that is a first fraction of a power supply voltage for the compute-in-memory and to provide a second reference voltage that is a second fraction of the power supply voltage for the compute-in-memory.
13 . The apparatus of claim 12 , wherein the voltage source is further configured so that the first fraction is approximately twice the second fraction.
14 . The apparatus of claim 1 , wherein the first switch comprises an n-type metal-oxide-semiconductor (NMOS) switch transistor and wherein the second switch comprises a p-type metal-oxide-semiconductor (PMOS) switch transistor.
15 . The apparatus of claim 1 , wherein the first switch comprises a p-type metal-oxide-semiconductor (PMOS) switch transistor and wherein the second switch comprises an n-type metal-oxide-semiconductor (NMOS) switch transistor.
16 . A method comprising:
charging a first plate of a capacitor responsive to a multiplication of a first activation bit signal with a first filter weight bit signal; and
charging a second plate of the capacitor responsive to a multiplication of a second activation bit signal with a second filter weight bit signal, wherein a voltage of the first plate is a tri-level voltage prior to accumulation as a multiple of a charged voltage of an arithmetic cell from a plurality of arithmetic cells.
17 . The method of claim 16 , wherein the charging of the first plate occurs during a first multiplication phase, the method further comprising:
coupling the first plate and the second plate to ground during a reset phase prior to the first multiplication phase.
18 . The method of claim 16 , wherein the charging of the first plate occurs during a first multiplication phase, the method further comprising:
coupling the second plate to ground during the first multiplication phase.
19 . The method of claim 18 , wherein the charging of the second plate occurs during a second multiplication phase that is subsequent to the first multiplication phase.
20 . The method of claim 19 , further comprising: accumulating a charge from the first plate onto a compute line subsequent to the second multiplication phase.
21 . The method of claim 20 , further comprising:
digitizing a voltage of the compute line following the accumulating of the charge from the first plate onto the compute line.
22 . An apparatus comprising:
a compute line; and
a plurality of arithmetic cells, wherein each arithmetic cell including:
a capacitor having a first plate and a second plate,
a first serial pair of switches coupled between the first plate and a voltage source to multiply a first filter weight bit signal with a first activation bit signal to charge the first plate,
a second serial pair of switches coupled between the second plate and the voltage source to multiply a second filter weight bit signal with a second activation bit signal to charge the second plate, and
a compute switch coupled between the first plate and the compute line, wherein a voltage of the first plate is a tri-level voltage prior to accumulation as a multiple of a charged voltage of an arithmetic cell from a plurality of arithmetic cells.
23 . The apparatus of claim 22 , further comprising:
an analog-to-digital converter having an input terminal coupled to the compute line.
24 . The apparatus of claim 23 , further comprising:
a digital adder coupled to an output terminal of the analog-to-digital converter.