Inserting a memory fence in a program in response to a determination that predetermined pattern(s) do not exist in the program

1 . A computer-implemented method, comprising:

determining whether a predetermined write pattern and a predetermined read pattern exist in a program of an application run on a hardware implementation;

in response to a determination that the predetermined write pattern and the predetermined read pattern do not exist in the program, inserting a memory fence before a variable in the program, wherein the insertion is performed by hardware of the hardware implementation; and

subsequent to the insertion of the memory fence, issuing instructions to cause the hardware of the hardware implementation to execute the program,

wherein an execution time of the program subsequent to the insertion of the memory fence before the variable in the program is relatively less than an execution time of the program before the insertion of the memory fence before the variable in the program, wherein the hardware of the hardware implementation is a processor,

wherein the determining whether the predetermined write pattern and the predetermined read pattern exist in the program of the application comprises issuing instructions to cause the hardware to perform at least one thread of execution in the program.

2 . The computer-implemented method of claim 1 , wherein the determination of whether the predetermined write pattern and the predetermined read pattern exist in the program of the application is performed in response to a determination that the application runs on a Power computing architecture.

3 . The computer-implemented method of claim 2 , wherein the variable of the program is a volatile variable, and comprising:

verifying a reduction in program execution time, wherein the verifying includes comparing the execution time of the program subsequent to the insertion of the memory fence before the variable in the program with the execution time of the program before the insertion of the memory fence before the variable in the program.

4 . The computer-implemented method of claim 3 , wherein the predetermined write pattern is a Store-Buffering (SB) pattern.

5 . The computer-implemented method of claim 4 , wherein the predetermined read pattern is an Independent Reads of Independent Writes (IRIW) pattern.

6 . The computer-implemented method of claim 3 , wherein inserting the memory fence before the variable in the program includes: inserting an acquire fence before a volatile read in the program.

7 . The computer-implemented method of claim 3 , comprising: in response to a determination that the predetermined write pattern and the predetermined read pattern exist in the program, inserting memory fences around variables in the program, wherein inserting memory fences around variables in the program includes: inserting a release fence before a volatile write in the program, inserting a release fence after the volatile write in the program, inserting a sequentially consistent fence before a volatile read in the program, and inserting an acquire fence after the volatile read in the program.

8 . The computer-implemented method of claim 1 , wherein the determination of whether the predetermined write pattern and the predetermined read pattern exist in the program of an application is performed along a program order, wherein the insertion performed by the hardware of the hardware implementation comprises performing read and write operations during operation of the application.

9 . The computer-implemented method of claim 1 , wherein static analysis is performed for determining whether the predetermined write pattern and the predetermined read pattern exist in the program of an application, wherein the static analysis includes: checking control flows to confirm that Store-Buffering (SB) and Independent Reads of Independent Writes (IRIW) patterns are not present in the program, wherein loops of the program are extracted only once during the checking of the control flows; and checking data flows to confirm volatile variables accesses and program orders associated therewith.

10 . A computer-implemented method comprising:

determining whether a predetermined write pattern exists in a program of an application run on a hardware implementation;

in response to a determination that the predetermined write pattern does not exist in the program, inserting a memory fence after a variable in the program, wherein the insertion is performed by hardware of the hardware implementation; and

subsequent to the insertion of the memory fence, issue instructions to cause the hardware of the hardware implementation to execute the program,

wherein an execution time of the program subsequent to the insertion of the memory fence before the variable in the program is relatively less than an execution time of the program before the insertion of the memory fence before the variable in the program, wherein the hardware of the hardware implementation is a processor,

wherein the determining whether the predetermined write pattern and the predetermined read pattern exist in the program of the application comprises issuing instructions to cause the hardware to perform at least one thread of execution in the program.

11 . The computer-implemented method of claim 10 , wherein the determination of whether the predetermined write pattern exists in the program of the application is performed in response to a determination that the application runs on a computing architecture other than a Power computing architecture.

12 . The computer-implemented method of claim 11 , wherein the variable of the program is a volatile variable, and comprising: verifying a reduction in program execution time, wherein the verifying includes comparing the execution time of the program subsequent to the insertion of the memory fence after the variable in the program with the execution time of the program before the insertion of the memory fence after the variable in the program.

13 . The computer-implemented method of claim 12 , wherein the predetermined write pattern is a Store-Buffering (SB) pattern.

14 . The computer-implemented method of claim 12 , wherein inserting the memory fence after the variable in the program includes: inserting a release fence after a volatile write in the program.

15 . The computer-implemented method of claim 12 , comprising: in response to a determination that the predetermined write pattern exists in the program, inserting memory fences around variables in the program, wherein inserting memory fences around variables in the program includes: inserting a release fence before a volatile write in the program, inserting a sequentially consistent fence after the volatile write in the program, inserting an acquire fence before a volatile read in the program, and inserting an acquire fence after the volatile read in the program.

16 . The computer-implemented method of claim 10 , wherein static analysis is performed for determining whether the predetermined write pattern exists in the program of an application, wherein the static analysis includes: checking control flows to determine whether the predetermined write pattern exists in the program, wherein loops of the program are extracted only once during the checking of the control flows; and checking data flows to confirm volatile variables accesses and program orders associated therewith.

17 . A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a computer to cause the computer to:

determine, by the computer, whether a predetermined write pattern and a predetermined read pattern exist in a program of an application run on a hardware implementation;

in response to a determination that the predetermined write pattern and the predetermined read pattern do not exist in the program, insert, by the computer, a memory fence before a variable in the program, wherein the insertion is performed by hardware of the hardware implementation; and

subsequent to the insertion of the memory fence, issue instructions to cause the hardware of the hardware implementation to execute the program,

wherein an execution time of the program subsequent to the insertion of the memory fence before the variable in the program is relatively less than an execution time of the program before the insertion of the memory fence before the variable in the program, wherein the hardware of the hardware implementation is a processor,

wherein the determining whether the predetermined write pattern and the predetermined read pattern exist in the program of the application comprises issuing instructions to cause the hardware to perform at least one thread of execution in the program.

18 . The computer program product of claim 17 , wherein the determination of whether the predetermined write pattern and the predetermined read pattern exist in the program of the application is performed in response to a determination that the application runs on a Power computing architecture.

19 . The computer program product of claim 18 , wherein the variable of the program is a volatile variable, and the program instructions readable and/or executable by the computer to cause the computer to: verify a reduction in program execution time, wherein the verifying includes comparing the execution time of the program subsequent to the insertion of the memory fence before the variable in the program with the execution time of the program before the insertion of the memory fence before the variable in the program.

20 . The computer program product of claim 19 , wherein the predetermined write pattern is a Store-Buffering (SB) pattern.