System and method for distributed forwarding logic for cyclic data-pipeline coherency

1 . A computer-implemented method, executed on a computing device, comprising:

processing data using a plurality of stages of a data processing pipeline;

identifying, based on a comparison of an input and an output of each stage of the plurality of stages, a data modification stage in the plurality of stages;

forwarding modified data from the data modification stage to each of the other stages of the plurality of stages, wherein each stage of the plurality of stages comprises selection logic to select between output data from a previous stage or the modified data from the data modification stage as input to an operator of the corresponding stage and wherein the modified data is provided as an input to the selection logic at each of the other stages;

at a respective stage in the plurality of stages, comparing an address of output data received from the previous stage relative to the respective stage with an address of the modified data;

in response to determining that the address of the output data from the previous stage is the same as the address of the modified data, selecting, using the selection logic, the modified data for processing in the respective stage; and

processing the modified data in the respective stage of the data processing pipeline.

2 . The computer-implemented method of claim 1 , wherein the data processing pipeline is executed using a field programmable gate array (FPGA).

3 . The computer-implemented method of claim 1 , wherein the data processing pipeline is executed using an application-specific integrated circuit (ASIC).

4 . The computer-implemented method of claim 1 , wherein processing the modified data in the respective stage of the data processing pipeline includes using the comparison of the address of the output data received from the previous stage with the address of the modified data as a control signal of a multiplexer to select an input signal for the respective stage.

5 . The computer-implemented method of claim 4 , wherein the input signal is one of the output data from the previous stage and the modified data.

6 . The computer-implemented method of claim 1 , wherein the data processing pipeline begins with reading the data from a memory location and ends with writing the modified data to the memory location.

7 . The computer-implemented method of claim 6 , further comprising:

identifying a first stage in the data processing pipeline;

identifying a first subsequent stage directly following the data modification stage;

forwarding input data from the first subsequent stage to the first stage;

comparing an address of output data received from the memory location with the address of the input data from the first subsequent stage; and

in response to determining that the address of the output data from the memory location is the same as the address of the input data from the first subsequent stage, processing the input data from the first subsequent stage in the first stage.

8 . A computing system comprising:

a memory; and

a computing device operatively coupled to the memory, the computing device configured to:

process data using a plurality of stages of a data processing pipeline;

identify, based on a comparison of an input and an output of each stage of the plurality of stages, a data modification stage in the plurality of stages;

forward modified data from the data modification stage to each of the other stages of the plurality of stages, wherein each stage of the plurality of stages comprises selection logic to select between output data from a previous stage or the modified data from the data modification stage as input to an operator of the corresponding stage and wherein the modified data is provided as an input to the selection logic at each of the other stages;

at each respective stage in the plurality of stages, compare an address of output data received from the previous stage relative to the respective stage with an address of the modified data;

in response to determining that the address of the output data from the previous stage is the same as the address of the modified data, select, using the selection logic, the modified data for processing in the respective stage; and

process the modified data in the respective stage of the data processing pipeline.

9 . The computing system of claim 8 , wherein the data processing pipeline is executed using a Field Programmable Gate Array (FPGA).

10 . The computing system of claim 8 , wherein the data processing pipeline is executed using an application-specific integrated circuit (ASIC).

11 . The computing system of claim 8 , wherein processing the modified data in the respective stage of the data processing pipeline includes using the comparison of the address of the output data received from the previous stage with the address of the modified data as a control signal of a multiplexer to select an input signal for the respective stage.

12 . The computing system of claim 11 , wherein the input signal is one of the output data from the previous stage and the modified data.

13 . The computing system of claim 8 , wherein the data processing pipeline begins with reading the data from a memory location and ends with writing the modified data to the memory location.

14 . The computing system of claim 13 , wherein the computing device is further configured to:

identify a first stage in the data processing pipeline;

identify a first subsequent stage directly following the data modification stage;

forward input data from the first subsequent stage to the first stage;

compare an address of output data received from the memory location with the address of the input data from the first subsequent stage; and

in response to determining that the address of the output data from the memory location is the same as the address of the input data from the first subsequent stage, process the input data from the first subsequent stage in the first stage.

15 . A non-transitory computer readable medium having instructions stored thereon which, when executed by a processor, cause the processor to:

process data using a plurality of stages of a data processing pipeline executed using a Field Programmable Gate Array (FPGA);

identify, based on a comparison of an input and an output of each stage of the plurality of stages, a data modification stage in the plurality of stages;

forward modified data from the data modification stage to each of the other stages of the plurality of stages, wherein each stage of the plurality of stages comprises selection logic to select between output data from a previous stage or the modified data from the data modification stage as input to an operator of the corresponding stage and wherein the modified data is provided as an input to the selection logic at each of the other stages;

at each respective stage in the plurality of stages, compare an address of output data received from the previous stage relative to the respective stage with an address of the modified data;

in response to determining that the address of the output data from the previous stage is the same as the address of the modified data, select, using the selection logic, the modified data for processing in the respective stage; and

process the modified data in the respective stage of the data processing pipeline.

16 . The non-transitory computer readable medium of claim 15 , wherein to process the modified data in the respective stage of the data processing pipeline the processor is further to use includes using the comparison of the address of the output data received from the previous stage with the address of the modified data as a control signal of a multiplexer to select an input signal for the respective stage.

17 . The non-transitory computer readable medium of claim 16 , wherein the input signal is one of the output data from the previous stage and the modified data.

18 . The non-transitory computer readable medium of claim 15 , wherein the data processing pipeline begins with reading the data from a memory location and ends with writing the modified data to the memory location.

19 . The non-transitory computer readable medium of claim 18 , wherein the processor is further configured to:

identify a first stage in the data processing pipeline;

identify a first subsequent stage directly following the data modification stage;

forward input data from the first subsequent stage to the first stage;

compare an address of output data received from the memory location with the address of the input data from the first subsequent stage; and

in response to determining that the address of the output data from the memory location is the same as the address of the input data from the first subsequent stage, process the input data from the first subsequent stage in the first stage.

20 . The non-transitory computer readable medium of claim 19 , wherein the processor is further configured to:

identify a second subsequent stage directly following the first subsequent stage;

forward input data from the second subsequent stage to the first stage;

compare an address of output data received from the memory location with the address of the input data from the second subsequent stage; and

in response to determining that the address of the output data from the memory location is the same as the address of the input data from the second subsequent stage, process the input data from the second subsequent stage in the first stage.