IP Library › Granted Patent US 12675314
Granted Patent B2
US 12675314 · App. 18/661,804 · Granted Jul 7, 2026

Streaming engine with short cut start instructions

Inventors: Timothy Anderson (University Park, TX); Joseph Zbiciak (San Jose, CA)
Assignee: TEXAS INSTRUMENTS INCORPORATED
G06F9/485G06F9/30014G06F9/30047G06F9/30145G06F9/345G06F9/383G06F15/76
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Quick Facts
Patent No.
US 12675314
App. No.
18/661,804
Granted
Jul 7, 2026
Kind
B2
Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

Claims (52)

1 . A device comprising:

a first memory configured to store a first set of data and a second set of data;

a circuit coupled to the first memory and configured to access the first set of data and the second set of data;

a second memory configured to store a first instruction to access the first set of data and a second instruction to access the second set of data, wherein:

the first instruction includes a first field that specifies a first value of a parameter for the first set of data;

the second instruction includes a second field that specifies a second value of the parameter for the second set of data;

a register file coupled to the circuit and including a first plurality of registers, the first plurality of registers including a first register configured to store the first value of the parameter for the first set of data; and

a decoder coupled to the second memory and configured to:

based on the first instruction, cause a first template associated with the first set of data and specifying the first value of the parameter to be provided to the circuit by accessing the register file and retrieving the first template from the first register, and cause the circuit to access a portion of the first set of data using the first template; and

based on the second instruction, cause a second template associated with the second set of data and specifying the second value of the parameter to be provided to the circuit without accessing the register file, and cause the circuit to access a portion of the second set of data using the second template.

2 . The device of claim 1 , wherein the parameter is a count of data elements.

3 . The device of claim 1 , wherein the parameter is a count of iterations of a loop.

4 . The device of claim 1 , further comprising a third memory coupled to the circuit, wherein:

the third memory is configured to store a table that includes an entry; and

the second field of second first instruction is configured to specify the parameter for the second set of data by specifying the entry from among the table.

5 . The device of claim 4 , wherein the third memory is a read-only memory.

6 . The device of claim 1 , wherein:

the first instruction specifies a start address for the first set of data; and

the second instruction specifies a start address for the second set of data.

7 . The device of claim 1 , wherein:

the circuit includes a first stream circuit and a second stream circuit;

the first instruction specifies which of the first stream circuit or the second stream circuit is to access the first set of data; and

the second instruction specifies which of the first stream circuit or the second stream circuit is to access the second set of data.

8 . The device of claim 1 , wherein the first field further specifies at least one of:

an element size of the first set of data or a promotion mode of the first set of data.

9 . The device of claim 1 , wherein the register file is a vector register file, and the first register is a first vector register that is configured to store the first template.

10 . The device of claim 6 , wherein the register file is a first register file and the device further comprises a second register file having a second plurality of registers including a second register, wherein:

the first register file is a vector register file and the first register is a first vector register configured to store the first template; and

the second register file is a scalar register file and the second register is a first scalar register configured to store the start address for the first set of data.

11 . The device of claim 10 , wherein the scalar register file comprises a second scalar register configured to store the start address for the second set of data.

12 . A device comprising:

a first memory configured to store a first set of data and a second set of data;

a circuit coupled to the first memory and configured to access the first set of data and the second set of data; and

a processor core that includes a decoder and a register file including a first plurality of registers, the first plurality of registers including a first register configured to store first template including a first value of a parameter for the first set of data, wherein the decoder is configured to:

based on a first instruction, cause the circuit to:

receive the first template from the first register of the register file;

access a portion of the first set of data using the first value of the first parameter for the first set of data from the first template; and

provide the portion of the first set of data to the processor core; and

based on a second instruction, cause the circuit to:

receive a second template without accessing the register file, the second template including a second value of the parameter for the second set of data;

access a portion of the second set of data using the second value of the first parameter for the second data set from the second template; and

provide the portion of the second set of data to the processor core, wherein the first field and the second field are different.

13 . The device of claim 12 further comprising a second memory coupled to the processor core and configured to store the first instruction and the second instruction.

14 . The device of claim 12 , wherein the parameter is a count of data elements.

15 . The device of claim 12 , wherein the parameter is a count of iterations of a loop.

16 . The device of claim 12 , further comprising a third memory coupled to the circuit, wherein:

the third memory is configured to store a table that includes an entry; and

the second field of second first instruction is configured to specify the parameter for the second set of data by specifying the entry from among the table.

17 . The device of claim 12 , wherein:

the circuit includes a first stream circuit and a second stream circuit;

the first instruction specifies which of the first stream circuit or the second stream circuit is to access the first set of data; and

the second instruction specifies which of the first stream circuit or the second stream circuit is to access the second set of data.