IP Library › Granted Patent US 12675356

Granted Patent B2

US 12675356 · App. 18/927,482 · Granted Jul 7, 2026

Debug and recovery operations for non-removable memory sub-systems

Inventors: Nicholas Terence Heath (Pittsboro, NC); Gaurav Sinha (Unterschleißheim, DE)

Assignee: Micron Technology, Inc.

G06F11/0778 G06F11/0727 G06F11/0775 G06F11/079 G06F11/0793 G06F11/2007 G06F21/79

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Quick Facts

Patent No.: US 12675356
App. No.: 18/927,482
Granted: Jul 7, 2026
Kind: B2

External Links

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Abstract

A processing device in a host system detecting a failure of a memory sub-system coupled to the host system and collects debug information from the memory sub-system via a memory sub-system interface. Responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system, the processing device performing an authentication process to authenticate the system to the memory sub-system, collects enhanced debug information from the memory sub-system via the memory sub-system interface, and performs one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.

Claims (57)

1 . A system comprising:

a memory sub-system interface; and

a processing device, operatively coupled with the memory sub-system interface, to perform operations comprising:

detecting a failure of a memory sub-system coupled to the memory sub-system interface;

collecting debug information from the memory sub-system via the memory sub-system interface;

determining whether the debug information is sufficient to correct the failure of the memory sub-system; and

responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:

performing an authentication process to authenticate the system to the memory sub-system; and

collecting enhanced debug information from the memory sub-system via the memory sub-system interface.

2 . The system of claim 1 , wherein the processing device is to perform operations further comprising:

performing one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.

3 . The system of claim 1 , wherein the memory sub-system interface comprises a primary in-band interface and a secondary side-band interface, each coupled between the system and the memory sub-system, and wherein the processing device is to perform operations further comprising:

determining whether the memory sub-system is responsive via the primary in-band interface; and

responsive to determining that the memory sub-system is responsive via the primary in-band interface, collecting the debug information from the memory sub-system via the primary in-band interface.

4 . The system of claim 3 , wherein the processing device is to perform operations further comprising:

responsive to determining that the memory sub-system is not responsive via the primary in-band interface, determining whether the memory sub-system is responsive via the secondary side-band interface; and

responsive to determining that the memory sub-system is responsive via the secondary side-band interface, collecting the debug information from the memory sub-system via the secondary side-band interface.

5 . The system of claim 4 , wherein the processing device is to perform operations further comprising:

responsive to determining that the debug information is sufficient to correct the failure of the memory sub-system, performing one or more corrective actions based on the debug information to correct the failure of the memory sub-system.

6 . The system of claim 1 , wherein the debug information comprises one or more of event log data, vendor specific log data, or self-monitoring and reporting technology log data from the memory sub-system.

7 . The system of claim 1 , wherein the enhanced debug information comprises one or more of log data or memory device state information from the memory sub-system and which is not accessible to unauthenticated requestors.

8 . The system of claim 1 , wherein performing the authentication process to authenticate the system to the memory sub-system comprises one or more of providing a password or security key, providing a cryptographic certificate, or establishing a secure communication session with the memory sub-system interface using a hardware security module.

9 . A method comprising:

detecting a failure of a memory sub-system coupled to a host system via a memory sub-system interface;

collecting debug information from the memory sub-system via the memory sub-system interface;

determining whether the debug information is sufficient to correct the failure of the memory sub-system; and

responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:

performing an authentication process to authenticate the host system to the memory sub-system; and

collecting enhanced debug information from the memory sub-system via the memory sub-system interface.

10 . The method of claim 9 , further comprising:

performing one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.

11 . The method of claim 9 , wherein the memory sub-system interface comprises a primary in-band interface and a secondary side-band interface, each coupled between the host system and the memory sub-system, and the method further comprising:

determining whether the memory sub-system is responsive via the primary in-band interface; and

responsive to determining that the memory sub-system is responsive via the primary in-band interface, collecting the debug information from the memory sub-system via the primary in-band interface.

12 . The method of claim 11 , further comprising:

13 . The method of claim 12 , further comprising:

14 . The method of claim 9 , wherein the debug information comprises one or more of event log data, vendor specific log data, or self-monitoring and reporting technology log data from the memory sub-system.

15 . The method of claim 9 , wherein the enhanced debug information comprises one or more of log data or memory device state information from the memory sub-system and which is not accessible to unauthenticated requestors.

16 . The method of claim 9 , wherein performing the authentication process to authenticate the host system to the memory sub-system comprises one or more of providing a password or security key, providing a cryptographic certificate, or establishing a secure communication session with the memory sub-system interface using a hardware security module.

17 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

detecting a failure of a memory sub-system coupled to a host system via a memory sub-system interface;

collecting debug information from the memory sub-system via the memory sub-system interface;

determining whether the debug information is sufficient to correct the failure of the memory sub-system; and

responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system:

performing an authentication process to authenticate the host system to the memory sub-system;

collecting enhanced debug information from the memory sub-system via the memory sub-system interface; and

performing one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the memory sub-system interface comprises a primary in-band interface and a secondary side-band interface, each coupled between the host system and the memory sub-system, and the instructions cause the processing device to perform operations further comprising:

determining whether the memory sub-system is responsive via the primary in-band interface; and

responsive to determining that the memory sub-system is responsive via the primary in-band interface, collecting the debug information from the memory sub-system via the primary in-band interface.

19 . The non-transitory computer-readable storage medium of claim 18 , wherein the instructions cause the processing device to perform operations further comprising:

20 . The non-transitory computer-readable storage medium of claim 17 , wherein the debug information comprises one or more of event log data, vendor specific log data, or self-monitoring and reporting technology log data from the memory sub-system, and wherein the enhanced debug information comprises one or more of log data or memory device state information from the memory sub-system and which is not accessible to unauthenticated requestors.