Controller-level memory repair
Described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. Each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. If a memory die has more faults than spare rows, the memory die cannot repair the additional faults. This document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. The controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. The controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.
1 . A method by a controller, the method comprising:
receiving a memory access request including an address;
determining that the address corresponds to a faulty address of a first memory die, the faulty address targeting a memory location including at least one faulty bit of the first memory die;
remapping the memory access request at least partially to a memory portion of a second memory die to produce a remapped memory access request responsive to the determining, the memory portion of the second memory die designated to provide redundancy for repairing at least one faulty address of one or more memory portions of the second memory die; and
transmitting to the second memory die the remapped memory access request based on the address of the memory access request and the memory location including the at least one faulty bit of the first memory die, the remapped memory access request targeting the memory portion that is designated to provide redundancy for repairing the at least one faulty address of the one or more memory portions of the second memory die.
2 . The method of claim 1 , further comprising:
receiving from the second memory die a memory access response including data corresponding to the address of the memory access request; and
transmitting the data upstream based on the receiving of the memory access request.
3 . The method of claim 1 , further comprising, prior to performing the remapping:
receiving from the first memory die at least one first indication that the first memory die has no redundant memory portions available for memory repair; and
receiving from the second memory die at least one second indication that the second memory die has at least one redundant memory portion available for memory repair, the at least one redundant memory portion including the memory portion of the second memory die designated to provide redundancy for repairing the at least one faulty address of the one or more memory portions of the second memory die.
4 . The method of claim 3 , further comprising:
producing at least one data structure that indicates one or more redundant memory portions that can be shared from one memory die to another memory die based on the at least one first indication and the at least one second indication; and
remapping the memory access request at least partially to the memory portion of the second memory die to produce the remapped memory access request using the at least one data structure.
5 . The method of claim 3 , further comprising, prior to performing the remapping:
transmitting to the first memory die a first request for one or more indications of at least one faulty memory location in the first memory die and at least a quantity of available redundant memory portions of the first memory die; and
transmitting to the second memory die a second request for one or more indications of at least one faulty memory location in the second memory die and at least a quantity of available redundant memory portions of the second memory die.
6 . The method of claim 1 , further comprising:
determining that the address of the memory access request corresponds to the faulty address of the first memory die based on the address of the memory access request and the faulty address of the first memory die at least partially matching.
7 . The method of claim 1 , wherein the controller comprises a memory controller, the method further comprising:
receiving, by the memory controller, the memory access request from a link controller that is configured to operate in accordance with at least one version of a Compute Express Link™ (CXL) protocol; and
transmitting, by the memory controller, data corresponding to the address of the memory access request upstream to the link controller based on the receiving of the memory access request from the link controller.
8 . The method of claim 1 , further comprising:
transmitting to the second memory die a signal indicating that the remapped memory access request is to be serviced using at least one redundant memory portion.
9 . The method of claim 8 , further comprising:
transmitting to the second memory die a command to write at least one bit into a mode register to enable access to the at least one redundant memory portion.
10 . An apparatus comprising:
an interface configured to be coupled to at least one bus that provides access to multiple memory dies; and
controller logic coupled to the interface; the controller logic configured to:
determine that an address of a memory access request corresponds to a faulty address of a first memory portion of a first memory die of the multiple memory dies, the faulty address targeting a memory location including at least one faulty bit of the first memory die;
remap the memory access request at least partially to a second memory portion of a second memory die of the multiple memory dies to produce a remapped memory access request responsive to the determination, the second memory portion of the second memory die designated to provide redundancy for repairing at least one faulty address of one or more memory portions of the second memory die; and
transmit to the second memory die the remapped memory access request based on the address of the memory access request and the memory location including the at least one faulty bit of the first memory die, the remapped memory access request targeting the second memory portion that is designated to provide redundancy for repairing the at least one faulty address of the one or more memory portions of the second memory die.
11 . The apparatus of claim 10 , wherein the controller logic is configured to:
receive from the first memory die one or more first indications of at least one faulty memory location in the first memory die and one or more second indications that the first memory die has no available redundant memory portions, the at least one faulty memory location corresponding to the faulty address of the first memory portion of the first memory die, the at least one faulty memory location comprising the memory location including the at least one faulty bit of the first memory die; and
receive from the second memory die one or more third indications of at least a quantity of one or more available redundant memory portions of the second memory die, the quantity greater than zero.
12 . The apparatus of claim 11 , further comprising:
at least one data structure that includes:
an entry comprising the faulty address of the first memory portion of the first memory die mapped to a repair indication including at least a portion of a repair address that identifies the second memory portion of the second memory die,
wherein the controller logic is configured to generate the at least one data structure based on the one or more first indications, the one or more second indications, and the one or more third indications.
13 . The apparatus of claim 10 , wherein the controller logic is configured to:
transmit a command to write at least one bit into a mode register to enable access to at least one redundant memory portion including the second memory portion of the second memory die.
14 . The apparatus of claim 10 , wherein:
the first memory portion comprises at least one of a memory row or a memory column of a first memory array of the first memory die; and
the second memory portion comprises at least one of a spare memory row or a spare memory column of a second memory array of the second memory die.
15 . The apparatus of claim 10 , wherein:
the first memory die and the second memory die are each part of at least one of different memory channels or different memory ranks.
16 . The apparatus of claim 10 , wherein:
the memory location including the at least one faulty bit of the first memory die comprises a faulty memory location of the first memory die; and
the faulty address is configured to identify the faulty memory location of the first memory portion of the first memory die of the multiple memory dies.
17 . The apparatus of claim 16 , wherein:
the first memory portion comprises a memory row of the first memory die;
the faulty address comprises a row address of the memory row;
the faulty memory location comprises the at least one faulty bit, which is part of the memory row; and
the second memory portion comprises a spare memory row of the second memory die.
18 . The apparatus of claim 10 , further comprising:
the at least one bus;
the multiple memory dies coupled to the at least one bus; and
front-end logic coupled to the controller logic and configured to:
be coupled to a bus that is external to the apparatus; and
receive the memory access request via the bus that is external to the apparatus.
19 . The apparatus of claim 18 , wherein:
the front-end logic is configured to comport with at least one version of a Compute Express Link™ (CXL) standard; and
the apparatus comprises a CXL memory device.
20 . An apparatus comprising:
a first interface configured to be coupled upstream to a component;
a second interface configured to be coupled downstream to multiple memory dies, the multiple memory dies comprising a first memory die and a second memory die; and
controller logic coupled to the first interface and the second interface,
the controller logic configured to:
receive from the component a memory access request including an address targeting a memory location of the first memory die, the memory location including at least one faulty bit; and
transmit to the second memory die a remapped memory access request based on the address of the memory access request and the memory location including the at least one faulty bit, the remapped memory access request targeting a memory portion that is designated to provide redundancy for repairing a faulty address of one or more memory portions of the second memory die.