IP Library › Granted Patent US 12675362
Granted Patent B2
US 12675362 · App. 18/191,401 · Granted Jul 7, 2026

Managing status output

Inventors: Chin-Hung Chang (Tainan, TW); Chia-Jung Chen (Zhubei, TW); Ken-Hui Chen (Hsinchu, TW)
Assignee: Macronix International Co., Ltd.
G06F11/1044
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Quick Facts
Patent No.
US 12675362
App. No.
18/191,401
Granted
Jul 7, 2026
Kind
B2
Abstract

Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

Claims (67)

1 . A semiconductor device comprising:

a memory array configured to store data; and

a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation in the memory array,

wherein the read operation is a secure read operation, and the read packet comprises an error code,

wherein the circuitry is configured to assign a value to the error code based on the result of the execution of the read operation in the memory array, different values of the error code indicating different types of errors associated with operations on the memory array, and

wherein the circuitry is configured to:

determine whether there is error occurrence on a first portion of the readout data;

in response to determining that there is error occurrence on the first portion of the readout data, assign a first value to the error code to indicate that there is error occurrence on the readout data, output the error code, without outputting the readout data,

in response to determining that there is no error occurrence on the first portion of the readout data, assign a second value different from the first value to the error code to indicate that there is no error occurrence on the first portion of the readout data, output the error code and the first portion of the readout data, and continue outputting a second portion of the readout data following the first portion of the readout data, and

in response to determining that there is error occurrence on the second portion of the readout data, configure at least one secure code to indicate that there is error occurrence on the readout data, and output the configured at least one secure code after the second portion of the readout data, wherein the at least one secure code comprises at least one of a message authentication code (MAC) of the readout data or a cyclic redundancy check (CRC) of the read packet.

2 . The semiconductor device of claim 1 , wherein the circuitry is configured to sequentially output the error code, the readout data, and one or more secure codes in the read packet, the one or more secure codes comprising the configured at least one secure code.

3 . The semiconductor device of claim 2 , wherein the error code indicates that there is no error associated with the readout data, and the configured at least one secure code indicates that there is an error associated with the readout data.

4 . The semiconductor device of claim 1 , wherein the circuitry is configured to:

generate the message authentication code (MAC) of the readout data; and

in response to determining that there is error occurrence on the second portion of the readout data, change the MAC to obtain a configured secure data code that is different from the MAC.

5 . The semiconductor device of claim 4 , wherein the circuitry is configured to change the MAC to obtain the configured secure data code by inverting the MAC with a logic, and

wherein the logic comprises at least one of an inverter or a XOR logic gate.

6 . The semiconductor device of claim 1 , wherein the circuitry is configured to:

generate the cyclic redundancy check (CRC) of the read packet; and

in response to determining that there is error occurrence on the second portion of the readout data, change the CRC to obtain a configured secure packet code that is different from the CRC.

7 . The semiconductor device of claim 6 , wherein the circuitry is configured to change the CRC to obtain the configured secure packet code by inverting the CRC with a logic, and

wherein the logic comprises at least one of an inverter or a XOR logic gate.

8 . The semiconductor device of claim 1 , wherein the circuitry is configured to output the error code after the readout data.

9 . The semiconductor device of claim 8 , wherein the circuitry is configured to sequentially output the readout data, MAC of the readout data, the error code, and CRC of the read packet in the read packet, and

wherein the error code indicates whether there is error occurrence on the readout data.

10 . The semiconductor device of claim 9 , wherein the CRC indicates whether there is error occurrence on the readout data.

11 . The semiconductor device of claim 1 , wherein the circuitry is configured to:

generate the error code in response to detecting a failure of error correction on the first portion of the readout data, and

wherein the secure read operation is configured to perform error detection and correction using error correction code (ECC), and wherein the circuitry is configured to set the first value for the error code in response to determining that the ECC fails to correct the first portion of the readout data.

12 . The semiconductor device of claim 1 , wherein the circuitry is configured to:

execute the read operation based on a request packet, wherein the request packet comprises information specifying the read operation.

13 . A system, comprising:

a semiconductor device comprising:

a memory array configured to store data; and

a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation,

wherein the read operation is a secure read operation, and the read packet comprises an error code,

wherein the circuitry is configured to assign a value to the error code based on the result of the execution of the read operation in the memory array, different values of the error code indicating different types of errors associated with operations on the memory array, and

wherein the circuitry is configured to:

determine whether there is error occurrence on a first portion of the readout data;

in response to determining that there is error occurrence on the first portion of the readout data, assign a first value to the error code to indicate that there is error occurrence on the readout data, output the error code, without outputting the readout data,

in response to determining that there is no error occurrence on the first portion of the readout data, assign a second value different from the first value to the error code to indicate that there is no error occurrence on the first portion of the readout data, output the error code and the first portion of the readout data, and continue outputting a second portion of the readout data following the first portion of the readout data, and

in response to determining that there is error occurrence on the second portion of the readout data, configure at least one secure code to indicate that there is error occurrence on the readout data, and output the configured at least one secure code after the second portion of the readout data, wherein the at least one secure code comprises at least one of a message authentication code (MAC) of the readout data or a cyclic redundancy check (CRC) of the read packet; and

a controller coupled to the semiconductor device and configured to receive the read packet from the semiconductor device,

wherein the controller is configured to detect whether there is error occurrence associated with the readout data based on the error code or the configured at least one secure code in the read packet.

14 . The system of claim 13 , wherein the controller is configured to:

receive the error code before the readout data and one or more secure codes in the read packet, the one or more secure codes comprising the configured at least one secure code; and

detect whether there is error occurrence associated with the readout data based on the configured at least one secure code in the read packet.

15 . The system of claim 14 , wherein the one or more secure codes comprise a secure data code based on the readout data, and

wherein the controller is configured to:

generate MAC of the readout data received in the read packet,

compare the generated MAC with the secure data code received in the read packet to determine whether the generated MAC is different from the secure data code received in the read packet, and

determine that there is an error associated with the readout data received in the read packet if the generated MAC is different from the secure data code received in the read packet.

16 . The system of claim 14 , wherein the one or more secure codes comprise a secure packet code based on the read packet, and

wherein the controller is configured to:

generate CRC of the read packet,

compare the generated CRC with the secure packet code received in the read packet to determine whether the generated CRC is different from the secure packet code received in the read packet, and

determine that there is an error associated with the readout data received in the read packet if the generated CRC is different from the secure packet code received in the read packet.

17 . The system of claim 13 , wherein the controller is configured to:

receive the error code after the readout data, and

detect whether there is error occurrence associated with the readout data based on the error code.

18 . A method comprising:

executing a read operation in a memory array storing data;

generating a read packet based on a result of executing the read operation, wherein the read operation is a secure read operation, and the read packet comprises an error code, different values of the error code indicating different types of errors associated with operations on the memory array;

determining whether there is error occurrence on a first portion of the readout data;

in response to determining that there is error occurrence on the first portion of the readout data, assigning a first value to the error code to indicate that there is error occurrence on the readout data, and outputting the error code, without outputting the readout data; or

in response to determining that there is no error occurrence on the first portion of the readout data, assigning a second value different from the first value to the error code to indicate that there is no error occurrence on the first portion of the readout data, outputting the error code and the first portion of the readout data, and continuing outputting a second portion of the readout data following the first portion of the readout data in the read packet; and

in response to determining that there is error occurrence on the second portion of the readout data, configuring at least one secure code to indicate that there is error occurrence on the readout data, and outputting the configured at least one secure code in the read packet after the second portion of the readout data, wherein the at least one secure code comprises at least one of a message authentication code (MAC) of the readout data or a cyclic redundancy check (CRC) of the read packet.