Internal memory error correction code information for memory systems

1 . A memory system, comprising:

one or more components configured to:

retrieve, via a first access operation, a block of user data,

wherein the block of user data is stored in a first portion of a memory associated with one or more data pins and is retrievable, during the first access operation, using the one or more data pins, and

wherein on-die error correction code (ECC) information associated with the block of user data is stored in a second portion of the memory associated with one or more data mask inversion (DMI) pins;

retrieve, via a second access operation, cyclic redundancy check (CRC) information associated with the block of user data as part of a mode in which data transfer via the one or more DMI pins is disabled,

wherein the CRC information is stored in a third portion of the memory associated with the one or more data pins and is retrievable, during the second access operation, using the one or more data pins; and

write, via a third access operation, updated CRC information to the third portion of the memory using a masked write command using the DMI pins as part of the mode in which data transfer via the one or more DMI pins is disabled.

2 . The memory system of claim 1 , wherein the block of user data and the CRC information are associated with a write command received from a host system.

3 . The memory system of claim 1 , wherein the one or more components are further configured to:

determine that the block of user data includes a bit error; and

correct the bit error using the on-die ECC information prior to retrieving the block of user data via the first access operation.

4 . The memory system of claim 1 , wherein the block of user data includes only 64 bytes of user data, and

wherein the CRC information includes only 32 bits of CRC information.

5 . The memory system of claim 1 , wherein the first access operation is associated with a first burst length quantity,

wherein the second access operation is associated with a second burst length quantity, and

wherein the second burst length quantity is less than the first burst length quantity.

6 . The memory system of claim 1 , wherein the first access operation is associated with a burst length 32 access operation, and

wherein the second access operation is associated with a burst length 16 access operation.

7 . The memory system of claim 1 , wherein the block of user data is associated with a reliability, availability, and serviceability (RAS) channel, and

wherein the RAS channel is associated with a CRC component that is capable of detecting errors in the block of user data, using the block of user data and the CRC information.

8 . The memory system of claim 1 , wherein the one or more components are further configured to correct, using a link ECC operation, one or more bit errors that occurred during a transmission of the block of user data.

9 . The memory system of claim 1 , wherein the one or more components are further configured to:

determine, using the CRC information, that the block of user data includes one or more bit errors; and

initiate a redundant array of independent disks error correction operation based on determining that that the block of user data includes one or more bit errors.

10 . A method, comprising:

retrieving, by a memory system controller via a first access operation, a block of user data,

wherein the block of user data is stored in a first portion of a memory associated with one or more data pins and is retrieved, during the first access operation, using the one or more data pins, and

wherein on-die error correction code (ECC) information associated with the block of user data is stored in a second portion of the memory associated with one or more data mask inversion (DMI) pins;

retrieving, by the memory system controller via a second access operation, cyclic redundancy check (CRC) information associated with the block of user data as part of a mode in which data transfer via the one or more DMI pins is disabled,

wherein the CRC information is stored in a third portion of the memory associated with the one or more data pins and is retrieved, during the second access operation, using the one or more data pins;

writing, by the memory controller and via a third access operation, updated CRC information to the third portion of the memory using a masked write command using the DMI pins as part of the mode in which data transfer via the one or more DMI pins is disabled; and

determining, by the memory system controller and using the block of user data and the CRC information, whether the block of user data includes one or more bit errors.

11 . The method of claim 10 , wherein the block of user data and the CRC information are associated with a write command received from a host system.

12 . The method of claim 10 , further comprising: determining, by an on-die ECC component, that the block of user data includes a bit error; and

correcting, by the on-die ECC component, the bit error using the on-die ECC information,

wherein correcting the bit error using the on-die ECC information by the on-die ECC component is performed prior to retrieving the block of user data by the memory system controller.

13 . The method of claim 10 , wherein the block of user data includes only 64 bytes of user data, and

wherein the CRC information includes only 32 bits of CRC information.

14 . The method of claim 10 , wherein the first access operation is associated with a first burst length quantity,

wherein the second access operation is associated with a second burst length quantity, and

wherein the second burst length quantity is less than the first burst length quantity.

15 . The method of claim 10 , wherein the first access operation is associated with a burst length 32 access operation, and

wherein the second access operation is associated with a burst length 16 access operation.

16 . The method of claim 10 , wherein the block of user data is associated with a reliability, availability, and serviceability (RAS) channel, and

wherein the RAS channel is associated with a CRC component that is capable of detecting errors in the block of user data using the block of user data and the CRC information.

17 . The method of claim 10 , further comprising correcting, using a link ECC operation, one or more bit errors that occurred during a transmission of the block of user data.

18 . The method of claim 10 , wherein determining whether the block of user data includes the one or more bit errors includes determining, using the block of user data and the CRC information, that the block of user data does include the one or more bit errors, and

wherein the method further comprises initiating, by the memory system controller, a redundant array of independent disks error correction operation based on determining that the block of user data does include the one or more bit errors.

19 . A compute express link (CXL) compliant memory system, comprising:

one or more components configured to:

retrieve, by a CXL controller and via a first access operation, a user data block (UDB),

wherein the UDB is stored in a first portion of a dynamic random access memory (DRAM) associated with one or more DQ pins and is retrievable, during the first access operation, using the one or more DQ pins, and

wherein on-die error correction code (ECC) information associated with the UDB is stored in a second portion of the DRAM associated with one or more data mask inversion (DMI) pins;

retrieve, via a second access operation, cyclic redundancy check (CRC) information associated with the UDB as part of a mode in which data transfer via the one or more DMI pins is disabled,

wherein the CRC information is stored in a third portion of the DRAM associated with the one or more DQ pins and is retrievable, during the second access operation, using the one or more DQ pins; and

write, by the CXL controller and via a third access operation, updated CRC information to the third portion of the DRAM using a masked write command using the DMI pins as part of the mode in which data transfer via the one or more DMI pins is disabled.

20 . The CXL compliant memory system of claim 19 , wherein the UDB and the CRC information are associated with a write command received from a CXL compliant host system.

21 . The CXL compliant memory system of claim 19 , wherein the one or more components are further configured to:

determine that the UDB includes a bit error; and

correct the bit error using the on-die ECC information prior to retrieving the UDB via the first access operation.

22 . The CXL compliant memory system of claim 19 , wherein the first access operation is associated with a first burst length quantity,

wherein the second access operation is associated with a second burst length quantity, and

wherein the second burst length quantity is less than the first burst length quantity.

23 . The CXL compliant memory system of claim 19 , wherein the UDB is associated with a reliability, availability, and serviceability (RAS) channel, and

wherein the RAS channel is associated with a CRC component that is capable of detecting errors in the UDB using the UDB and the CRC information.

24 . The CXL compliant memory system of claim 19 , wherein the one or more components are further configured to correct, using a link ECC operation, one or more bit errors that occurred during a transmission of the block of user data.

25 . The CXL compliant memory system of claim 19 , wherein the one or more components are further configured to:

determine, using the UDB and the CRC information, that the UDB includes one or more bit errors; and

initiate a redundant array of independent disks error correction operation based on determining that the UDB includes the one or more bit errors.