Apparatus and methods for recovering power on read failing die
An apparatus is provided that includes a first memory die including first corresponding initialization information and a first data latch, and a first control circuit coupled to the first memory die. The first control circuit is configured to send a power on read command to the first memory die, determine that the first memory die reported a power on read failure, retrieve a first backup copy of the first corresponding initialization information from a first storage location outside the first memory die, and load the retrieved first backup copy of the first corresponding initialization information to the first data latch.
1 . An apparatus comprising:
a first memory die comprising first corresponding initialization information and a first data latch; and
a first control circuit coupled to the first memory die, the first control circuit configured to:
send a power on read command to the first memory die;
determine that the first memory die reported a power on read failure;
retrieve a first backup copy of the first corresponding initialization information from a first storage location outside the first memory die; and
load the retrieved first backup copy of the first corresponding initialization information to the first data latch,
wherien the first data latch is for initialization and backup.
2 . The apparatus of claim 1 , wherein:
the apparatus comprises a first memory system comprising the first memory die and a second memory die; and
the first storage location comprises the second memory die.
3 . The apparatus of claim 1 , wherein:
the apparatus comprises a first memory system comprising the first memory die and a second memory system comprising a second memory die; and
the first storage location comprises the second memory die.
4 . The apparatus of claim 1 , wherein:
the apparatus comprises a first memory system comprising the first memory die and the first control circuit; and
the first storage location comprises the first control circuit.
5 . The apparatus of claim 1 , wherein:
the apparatus comprises a first memory system comprising the first memory die and a second memory system comprising a second control circuit; and
the first storage location comprises the second control circuit.
6 . The apparatus of claim 1 , wherein the first control circuit is further configured to perform a test memory operation of the first memory die to determine if the first memory die correctly initialized.
7 . The apparatus of claim 1 , wherein the first control circuit is further configured to:
determine that the first memory die successfully initialized; and
relocate user data from the first memory die to a second memory die.
8 . The apparatus of claim 1 , wherein the first control circuit is further configured to:
determine that the first memory die successfully initialized; and
save new first corresponding initialization information on the first memory die.
9 . The apparatus of claim 8 , wherein the new first corresponding initialization information comprises the first backup copy of the first corresponding initialization information.
10 . The apparatus of claim 8 , wherein:
the first memory die comprises a block of memory cells configured to store test data and a second backup copy of the first initialization information;
the new first corresponding initialization information comprises the second backup copy of the first corresponding initialization information.
11 . The apparatus of claim 1 , wherein:
the apparatus comprises a memory system comprising the first memory die and the first control circuit; and
the first control circuit is further configured to:
determine that the first memory die did not successfully initialize; and
report a failure of the memory system.
12 . The apparatus of claim 1 , wherein the first data latch comprises an interface latch configured to store data from the first control circuit.
13 . A memory system comprising:
a first memory die comprising a first block of memory cells comprising first corresponding initialization information for the first memory die, a first data latch, and a second block of memory cells; and
a second memory die comprising a third block of memory cells comprising second corresponding initialization information for the second memory die, a second data latch and a fourth block of memory cells,
wherein:
the second block of memory cells comprises a first backup copy of the second corresponding initialization information,
wherien the first data latch is for initialization and backup,
wherien the second data latch is for initialization and backup; and
the fourth block of memory cells comprises a first backup copy of the first corresponding initialization information.
14 . The memory system of claim 13 , wherein:
the first block of memory cells is programmed with the first corresponding initialization information at the same time that the fourth block of memory cells is programmed with the first backup copy of the first corresponding initialization information; and
the third block of memory cells is programmed with the second corresponding initialization information at the same time that the second block of memory cells is programmed with the first backup copy of the second corresponding initialization information.
15 . The memory system of claim 14 , wherein the first block of memory cells, the second block of memory cells, the third block of memory cells and the fourth block of memory cells are programmed during manufacture and testing of the first memory die and the second memory die.
16 . The memory system of claim 14 , wherein the first block of memory cells, the second block of memory cells, the third block of memory cells and the fourth block of memory cells are programmed prior to the first memory die and the second memory die being deployed for use by a user.
17 . The memory system of claim 13 , further comprising a memory controller coupled to the first memory die and the second memory die, the memory controller configured to:
send a power on read command to the first memory die;
determine that the first memory die reported a power on read failure;
retrieve the first backup copy of the first corresponding initialization information from the fourth block of memory cells; and
load the retrieved first backup copy of the first corresponding initialization information to the first data latch on the first memory die.
18 . The memory system of claim 17 , wherein the memory controller is further configured to:
determine that the first memory die successfully initialized; and
relocate user data from the first memory die to another memory die in the memory system.
19 . The memory system of claim 17 , wherein the memory controller is further configured to:
determine that the first memory die successfully initialized; and
save new first corresponding initialization information on the first memory die.
20 . A method comprising:
manufacturing a first non-volatile memory die and a second non-volatile memory die;
determining first initialization parameters for the first non-volatile memory die;
determining second initialization parameters for the second non-volatile memory die;
programming a first block of memory cells of the first non-volatile memory die with the first initialization parameters;
programming a second block of memory cells of the first non-volatile memory die with the second initialization parameters;
programming a first block of memory cells of the second non-volatile memory die with the second initialization parameters; and
programming a second block of memory cells of the second non-volatile memory die with the first initialization parameters,
wherein:
the first initialization parameters are configured to load the first non- volatile memory die into a first data latch in response to a power on read command; and
the second initialization parameters are configured to load the second non- volatile memory die into a second data latch in response to the power on read command,
wherien the first data latch is for initialization and backup, and
wherien the second data latch is for initialization and backup.