Memory controller for scheduling commands, storage device including memory controller, and operating method of memory controller
A storage device includes a memory device including a plurality of dies and a memory controller receiving at least one command from a host and transferring the at least one command to the memory device, wherein the memory controller stores commands received from the host in a queue, and when there are commands that occupy the same die among the commands stored in the queue, the memory controller changes an order in which the commands are transferred to the memory device.
1 . A storage device that communicates with a host, the storage device comprising:
a memory device including a plurality of dies; and
a memory controller configured to receive at least one command from the host and transfer the at least one command to the memory device,
wherein the memory controller is configured to store commands received from the host in a queue, and
wherein, based on a first set of commands, among the commands stored in the queue, that occupy the same die, the memory controller is configured to change an order in which the commands stored in the queue are transferred to the memory device so that the first set of commands that occupy the same die are transferred one after another in consecutive order.
2 . The storage device of claim 1 , wherein the memory controller is configured to change the order so that commands of a same command type among the first set of commands that occupy the same die are transferred one immediately after another in consecutive order.
3 . The storage device of claim 1 , wherein the memory controller is configured to determine whether to store the at least one command received from the host in the queue based on a queue depth.
4 . The storage device of claim 3 , wherein, in response to the queue depth for the at least one command corresponding to a first queue depth, the memory controller is configured to store the commands in the queue and to change the order of the commands stored in the queue.
5 . The storage device of claim 4 , wherein, in response to the queue depth for the at least one command corresponding to a second queue depth less than the first queue depth, the memory controller is configured to directly transfer the at least one command to the memory device.
6 . The storage device of claim 1 , wherein the memory controller is configured to calculate a total amount of power of the memory device and to transfer the commands stored in the queue to the memory device in the changed order based on the total amount of power of the memory device.
7 . The storage device of claim 6 , wherein, in response to the total amount of power of the memory device being less than a limited power amount of the memory device, the memory controller is configured to transfer at least one of the commands stored in the queue to the memory device according to the changed order.
8 . The storage device of claim 1 , wherein the memory controller is configured to compare a total amount of power of the memory device with a limited power amount of the memory device and to change the order in response to there being commands that occupy the same die among the commands stored in the queue according to a comparison result.
9 . The storage device of claim 1 , wherein the memory controller is configured to receive die state information from the memory device and to change the order based on the die state information.
10 . A memory controller comprising:
a queue controller circuit configured to determine whether to store a command received from a host in a queue based on a queue depth;
a scheduler circuit configured to generate a scheduling program for providing commands to a memory device including a plurality of dies, based on whether there is an overlapping die among the plurality of dies respectively occupied by the commands stored in the queue and whether the commands are stored in the queue; and
a power counter circuit configured to compare a total amount of power of the memory device with a limited power amount of the memory device and generate a power comparison result,
wherein the scheduler circuit is configured to transfer at least one of the commands to the memory device according to the scheduling program based on the power comparison result, and
wherein the scheduling program is configured to set the commands that occupy the overlapping die in consecutive order for being transferred one after another in response to the commands being provided to the memory device.
11 . The memory controller of claim 10 , wherein the queue controller circuit is configured to store the command received from the host in the queue in response to the queue depth for the command received from the host being greater than or equal to a threshold depth, and
wherein the scheduler circuit is configured to generate the scheduling program based on whether there is an overlapping die.
12 . The memory controller of claim 10 , wherein the queue controller circuit is configured to bypass storing the command received from the host in the queue in response to the queue depth for the command received from the host being less than a threshold depth.
13 . The memory controller of claim 10 , wherein the power counter circuit calculates the total amount of power based on a type of command performed by the memory device and a number of commands performed by the memory device.
14 . The memory controller of claim 10 , wherein the scheduler circuit transfers at least one of the commands stored in the queue according to the scheduling program based on the power comparison result being that the total amount of power is less than the limited power amount.
15 . The memory controller of claim 10 , wherein, in response to the power comparison result being that the total amount of power is greater than or equal to the limited power amount, the scheduler circuit is configured to stop transferring at least one of the commands stored in the queue to the memory device according to the scheduling program.
16 . The memory controller of claim 10 , wherein, in response to the power comparison result being that the total amount of power is greater than or equal to the limited power amount, the scheduler circuit is configured to re-generate the scheduling program.
17 . An operating method of a memory controller, the operating method comprising:
receiving at least one command from a host;
determining whether to store the at least one command in a queue;
generating a scheduling program for providing commands to a memory device, based on whether the commands are stored in the queue and whether there is an overlapping die among a plurality of dies respectively occupied by the commands stored in the queue, wherein the scheduling program is configured to set the commands that occupy the overlapping die in consecutive order for being transferred one after another in response to the commands being provided to the memory device; and
transferring at least one of the commands to the memory device according to the scheduling program.