Chiplet architecture data processing devices and methods
A data processing device incorporates a plurality of chiplets having working elements such as processing and memory elements. At least one of the working elements is operative to generate messages directed to working elements of the same chiplet or another one of the chiplets. Each message includes a global address. An evaluation circuit determines whether the global address of a message is within a range of global addresses assigned to the chiplet. If so, the message passes to a translation circuit which translates the message to a local address for routing to a working element of the chiplet. If not, the message is dispatched to one or more other chiplets.
1 . A chiplet comprising:
a plurality of working elements, at least one of the working elements being responsive to software commands to process data; and
one or more circuits operative to:
provide one or more values defining a chiplet range of global addresses for the chiplet, the chiplet range being mutually exclusive with the chiplet range for any other interconnected chiplets;
receive a message including a payload and a global address within a global range of global addresses from the any other interconnected chiplets;
when the global address of the message is within the chiplet range, translate the global address of received message to a local address, and
route the payloads of messages to working elements within the chiplet responsive to the local addresses;
when the global address of the message is outside the chiplet range, dispatch the message to one or more other ones of the interconnected chiplets.
2 . The chiplet of claim 1 , wherein the one or more circuits are operative to accept messages from the other interconnected chiplets, and, when the global address of a message received from another interconnected chiplet is within the chiplet range, pass the message to a translation circuit.
3 . The chiplet of claim 1 , wherein when the global address of the message is outside the chiplet range, the one or more circuits are configured to dispatch the message to all of the other chiplets in the plurality of chiplets.
4 . The chiplet of claim 2 , wherein when the global address of the message is outside the chiplet range, the one or more circuits are configured to ignore the message.
5 . The chiplet of claim 1 , wherein the one or more circuits are connected to an identification conductor.
6 . The chiplet of claim 5 , wherein the one or more circuits determine the chiplet range for the chiplet from the identity of the connected identification conductor.
7 . The chiplet of claim 1 , wherein the one or more circuits includes a register for holding one or more user-defined parameters, wherein the one or more circuits are operative to define the chiplet range based on the user-defined parameters.
8 . The chiplet of claim 1 , wherein the one or more circuits comprise a range circuit, a translation circuit, a local routing circuit, and an evaluation circuit.
9 . A data processing device, comprising:
a plurality of chiplets interconnected to one another, each one of the chiplets having an associated chiplet range of global addresses, the chiplet range for each one of the plurality of chiplets being mutually exclusive with the chiplet range for any other one of the plurality of chiplets, the each one of the chiplets comprising:
a plurality of working elements, at least one of the working elements being responsive to software commands to process data and generate messages, each message including a payload and a global address within a global range of global addresses; and
one or more circuits operative to:
when the global address of a message from one of the a plurality of working element of the chiplet is within the chiplet range, pass the message to a translation circuit of the chiplet; and
when the global address of a message from one of the a plurality of working element of the chiplet is outside the chiplet range, dispatch the message to one or more other ones of the plurality of chiplets.
10 . The device of claim 9 , wherein the one or more circuits of each chiplet is operative to accept messages from the other ones of the plurality of chiplets, and, when the global address of one of the messages received from another one of the plurality of chiplets is within the chiplet range, pass the one of the messages to the translation circuit.
11 . The device of claim 9 , wherein the plurality of chiplets includes at least three chiplets arranged in an ordered array having first and second opposite directions, with each chiplet being directly connected to at least one neighboring chiplet in at least one of the first and second directions.
12 . The device of claim 11 , wherein at least one chiplet is directly connected to a next neighboring chiplet in the first direction and directly connected to another next neighboring chiplet in the second direction.
13 . The device of claim 12 , wherein an evaluation circuit of each chiplet is operative to dispatch messages having global addresses above the chiplet range to a next neighboring chiplet in the first direction and to dispatch messages having global addresses below the chiplet range to a next neighboring chiplet in the second direction.
14 . The device of claim 11 , wherein the array is a linear array having opposite ends and wherein chiplets at opposite ends of the array are interconnected with one another only through one or more chiplets between the ends.
15 . The device of claim 11 , wherein the array is a ring array, wherein every chiplet in the array is directly connected to a next neighboring chiplet in the first direction and directly connected to another next neighboring chiplet in the second direction.
16 . The device of claim 9 , wherein an evaluation circuit of each chiplet is operative to, when a message received from a working element of the chiplet is outside the chiplet range, dispatch the message to all of the other chiplets in the plurality of chiplets.
17 . The device of claim 16 , wherein the evaluation circuit of each chiplet is operative to, when a message received from another chiplet is outside the chiplet range, ignore the message.
18 . The device of claim 9 , comprising a plurality of identification conductors, and wherein a range circuit of each chiplet is connected to a different one of the plurality of identification conductors, the range circuit of each chiplet including a circuit for determining the chiplet range for the chiplet from the identity of the connected identification conductor.
19 . The device of claim 10 , wherein the one or more circuits of each chiplet includes a register for holding one or more user-defined parameters and are operative to define the chiplet range based on the user-defined parameters.