Differentiated QoS in parallel cached RAS channels in memory devices
A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.
1 . A memory device comprising:
a plurality of memory media devices and a plurality of backend interfaces, wherein the backend interfaces are configured to connect to respective ones of the memory media devices;
a plurality of reliability, availability and serviceability (RAS) channel datapaths, wherein each of the RAS channel datapaths of the plurality of RAS channel datapaths is connected to one or more of the plurality of backend interfaces;
one or more caches, wherein at least one of the one or more caches is connected to at least one RAS channel datapath of the plurality of RAS channel datapaths; and
control circuitry configured to:
search a given cache, of the one or more caches, for a requested memory location in response to receiving a memory access request from a host; and
when the requested memory location is not found in the given cache during the search of the given cache, obtain the requested memory location from a given memory media device of the plurality of memory media devices, each given memory media device of the plurality of memory media devices including within its structure its own dedicated RAS channel datapath of the plurality of RAS channel datapaths also connected to the given cache;
wherein the control circuitry is further configured to, when obtaining a requested memory from the given memory media device:
obtain, from the given memory media device, a plurality of data blocks and one block of error correction data corresponding to the plurality of data blocks, wherein the requested memory location is in one of the plurality of data blocks;
integrity checking, by the dedicated RAS channel datapath, of the plurality of RAS channel datapaths, included within its memory media device, the plurality of data blocks using the one block of error correction data; and
storing the plurality of data blocks in the one or more caches.
2 . The memory device according to claim 1 , wherein the search of the given cache comprises identifying the given cache based on a virtual channel, and wherein the given memory media device is mapped to the virtual channel.
3 . The memory device according to claim 2 , wherein the control circuitry is configured to determine the virtual channel in accordance with a virtual channel identifier in a protocol header of the memory access request.
4 . The memory device according to claim 3 , wherein the virtual channel identifier is determined by the host in accordance with a memory address associated with the memory access request.
5 . The memory device according to claim 1 , wherein the control circuitry is configured to, when, in response to the search, the requested memory location is found in the one or more caches, return the requested memory location to a requester.
6 . The memory device according to claim 1 , wherein the plurality of memory media devices comprise dynamic random access memory (DRAM) media devices.
7 . The memory device according to claim 6 , wherein the plurality of memory media devices comprise low power double data rate DRAM media devices.
8 . The memory device according to claim 1 , wherein each of RAS channel datapath of the plurality of RAS channel datapaths is mapped to a respective virtual channel of a plurality of virtual channels.
9 . The memory device according to claim 8 , further comprising credit control circuitry configured to separately control credits for each virtual channel of the plurality of virtual channels.
10 . The memory device according to claim 9 , wherein the credit control circuitry is configured to separately control the credits based on an occupancy level of at least one of a cache and respective buffers storing received memory access requests.
11 . The memory device according to claim 9 , wherein the credit control circuitry is configured to separately control the credits based on predetermined respective quality of service configurations for respective ones of the plurality of virtual channels.
12 . The memory device according to claim 9 , wherein the separate control of the credits is in accordance with a transaction layer function of a memory protocol.
13 . The memory device according to claim 9 , wherein the separate control of the credits includes communicating a credit availability level of a given virtual channel of the plurality of virtual channels to an originator of the memory access request.
14 . The memory device according to claim 1 , wherein the one or more caches comprise a plurality of caches, and wherein the plurality of caches are connected to respective ones of the plurality of RAS channel datapaths.
15 . The memory device according to claim 1 , wherein the memory access request is one of a plurality of requests in a flit received from the host, and wherein the control circuitry is configured to extract a header of the memory access request from a slot in the flit.
16 . A method performed by control circuitry of a memory device, the method comprising:
in response to receiving, from a host, a memory access request for a memory location, searching a given cache, of one or more caches arranged on the memory device, for the requested memory location; and
when, in response to the search, the requested memory location is not found in the given cache, obtaining the requested memory location from a given memory media device, each given memory media device including within its structure its own dedicated reliability, availability and serviceability (RAS) channel datapath of a plurality of RAS channel datapaths arranged on the memory device,
wherein the memory device comprises a plurality of backend interfaces and a plurality of memory media devices including the given memory media device, each backend interface being configured to connect to a respective one of the plurality of memory media devices, wherein each of the plurality of RAS channel datapaths is connected to one or more of the plurality of backend interfaces, and wherein each of the one or more caches is connected to at least one of the plurality of RAS channel datapaths;
wherein the obtaining of the requested memory location from the given memory media comprises:
obtaining, from the given memory media device, a plurality of data blocks and one block of error correction data corresponding to the plurality of data blocks, wherein the requested memory location is in one of the plurality of data blocks;
integrity checking, by the dedicated RAS channel datapath of the plurality of RAS channel datapaths included within the structure of its memory media device, the plurality of data blocks using the one block of error correction data; and
storing the plurality of data blocks in a given one or more caches, of the one or more caches, connected to the dedicated RAS channel datapath of the plurality of RAS channel datapaths.
17 . The method according to claim 16 , wherein said searching a given cache of the one or more caches arranged on the memory device for the requested memory location comprises identifying the cache for access based on a virtual channel, and wherein the media device is mapped to the virtual channel.