Memory module with local clock signals
A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and to generate a module clock signal and module C/A signals in response to the system clock and input C/A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.
1 . A memory module operable in a computer system having a memory controller and a system bus, the system bus including one or more clock signal lines, control/address (C/A) signal lines and data signal lines, the memory module comprising:
a printed circuit board (PCB) having connectors configured to provide electrical connections between the memory module and the system bus;
memory devices mounted on the PCB and organized in a plurality of groups, wherein a respective group of the memory devices is configurable to communicate data with the memory controller via a corresponding subset of the data signal lines;
circuitry mounted on the PCB and configurable to:
receive from the memory controller a system clock via the one or more clock signal lines and input control and address (C/A) signals via the C/A signal lines;
generate module C/A signals in response to the input C/A signals;
generate a plurality of local clocks corresponding, respectively, to the plurality of groups of the memory devices, the plurality of local clocks having respective phase relationships with the system clock, the respective phase relationships being programmable independently of each other; and
output the module C/A signals to the memory devices; and
output the plurality of local clocks to the memory devices, wherein a respective local clock having a respective programmable phase relationship with the system clock is output to a corresponding group of the memory devices and not to any other group of the memory devices, wherein the corresponding group of the memory devices is configurable to perform memory read or write operations by communicating data signals with the memory controller via a corresponding subset of data signal lines in accordance with the respective local clock.
2 . The memory module of claim 1 , wherein the circuitry includes logic and configuration registers programmable by the logic to control the respective phase relationships.
3 . The memory module of claim 2 , wherein:
the memory module is operable in at least a normal operation mode and a configuration mode;
the memory module in the normal operation mode is configurable to output or receive data signals via the data signal lines in response to memory read or write commands received via the C/A signal lines; and
the memory module in the configuration mode is configurable to perform one or more operations to program the respective configuration registers.
4 . The memory module of claim 3 , wherein the memory module is configurable to perform the one or more operations in response to mode register command signals received from the memory controller.
5 . The memory module of claim 2 , wherein the circuitry further includes phase-locked loop circuit (PLL) circuitry to provide phase locking between the system clock and the plurality of local clocks, programmable delay circuitry to add respective delays to respective ones of the plurality of local clocks, and clock driver circuitry to drive the plurality of local clocks to the memory devices, the respective delays being controlled by respective registers that are programmable independently of each other.
6 . A memory module operable in a computer system having a memory controller and a system bus, the system bus including one or more clock signal lines, control/address (C/A) signal lines and data/strobe signal lines, the memory module comprising:
a printed circuit board (PCB) having connectors configured to provide electrical connections between the memory module and the system bus;
memory devices mounted on the PCB, the memory devices including first memory devices and second memory devices;
circuitry on the PCB and coupled to the memory devices, wherein the circuitry is configurable to:
receive from the memory controller a system clock via the one or more clock signal lines and input control and address (C/A) signals via the C/A signal lines;
generate module C/A signals in response to the input C/A signals;
generate local clocks from the system clock, the local clocks including a first local clock having a first phase shift from the system clock and a second local clock having a second phase shift from the system clock, the first phase shift and the second phase shift being programmable independently of each other; and
output the module C/A signals to the memory devices; and
output the local clocks to the memory devices, wherein the first local clock is output to the first memory devices and not to any of the memory devices other than the first memory devices, the second local clock is output to the second memory devices and not to any of the memory devices other than the second memory devices, and wherein the first memory devices are configurable to perform memory read or write operations by communicating data/strobe signals in accordance with the first local clock via a first subset of the data/strobe signal lines, and the second subset of the memory devices are configurable to perform memory read or write operations by communicating data/strobe signals in accordance with the second local clock via a second subset of the data/strobe signal lines.
7 . The memory module of claim 6 , wherein the circuitry includes logic and configuration registers programmable by the logic, the registers including one or more first registers to control the first phase shift and one or more second registers to control the second phase shift.
8 . The memory module of claim 7 , wherein:
the memory module is operable in at least a normal operation mode and a configuration mode;
the memory module in the normal operation mode is configurable to output or receive data/strobe signals via the data/strobe signal lines in response to memory read or write commands received via the C/A signal lines; and
the memory module in the configuration mode is configurable to perform one or more operations to program the configuration registers.
9 . The memory module of claim 8 , wherein the memory module is configurable to perform the one or more operations in response to mode register command signals received from the memory controller.
10 . The memory module of claim 7 , wherein the circuitry further includes phase-locked loop circuit (PLL) circuitry to provide phase locking between the system clock and the local clocks, programmable delay circuitry to add respective delays to respective ones of the local clocks, and clock driver circuitry to drive the local clocks to the memory devices, the respective delays being controlled by respective registers that are programmable independently of each other.
11 . The memory module of claim 1 , wherein:
the connectors including C/A connectors corresponding, respectively, to the C/A signal lines, and data connectors corresponding, respectively, to the data signal lines;
the input C/A signals include first input C/A signals for a memory write operation to write first data to the memory module;
the circuitry includes a module control device mounted on the PCB and configurable to receive the input C/A signals via the C/A connectors, and to output first module C/A signals and first module control signals for the write operation in response the first input C/A signals;
the circuitry further includes a plurality of data buffers mounted on the PCB and coupled to the module control device;
each data buffer of the plurality of data buffers is coupled between a respective subset of the data connectors and a corresponding group of the memory devices;
the first data has a bit width of N and includes m n-bit-wide sections corresponding, respectively, to m subsets of the data signal lines and to m data buffers of the plurality of data buffers, N=mxn, wherein n and m are integers greater than 1;
a respective data buffer of the m data buffers is configurable to receive the first module control signals and to receive a corresponding n-bit-wide section of the first data in response to the first module control signals;
the respective data buffer is further configurable to transmit the corresponding n-bit-wide section of the first data to at least a first branch of memory devices in the group of the memory devices coupled to the respective data buffer;
the respective data buffer is further configurable to generate a respective local clock and to transmit the respective local clock to at least the first branch of memory devices; and
at least one first memory device in the first branch of memory devices is configurable to receive at least some of the first module C/A signals and the respective local clock, and to receive and store the corresponding n-bit-wide section of the first data in response to the at least some of the first module C/A signals and in accordance with the respective local clock.
12 . The memory module of claim 11 , wherein:
the module control device is further configurable to receive the system clock and to output a module clock; and
the each respective data buffer of the m data buffers is further configured to receive the module clock and to generate the respective local clock from the module clock, the respective local clock having a respective phase shift from the module clock.
13 . The memory module of claim 12 , wherein the each respective data buffer includes logic and respective configuration registers programmable by the logic, and wherein the respective phase shift is dependent on one or more register settings in the respective configuration registers.
14 . The memory module of claim 13 , wherein:
the memory module is operable in at least a normal operation mode and a configuration mode;
the write operation is performed in the normal operation mode; and
the respective configuration registers are programmed in one or more operations during the configuration mode.
15 . The memory module of claim 14 , wherein the memory module is configurable to perform the one or more operations in response to mode register command signals received from the memory controller.
16 . The memory module of claim 12 , wherein:
the m data buffers include a first data buffer and a second data buffer;
the first data buffer is configurable to generate a first local clock from the module clock in response to the module control signals and to transmit the first local clock to at least a first branch of a first section of memory devices;
the second data buffer is configurable to generate a second local clock from the module clock in response to the module control signals and to transmit the second local clock to at least a first branch of a second section of memory devices;
the first local clock has a first phase shift from the module clock;
the second local clock has a second phase shift from the module clock; and
the first shift and the second phase shift are programmable independently of each other.
17 . The memory module of claim 11 , wherein:
the each respective data buffer of the m data buffers includes a first n-bit-wide write path coupled to the first branch of the respective section of the memory device and not to a second branch of the respective section of the memory device, and a second n-bit-wide write path coupled to the second branch of the respective section of the memory device and not to the first branch of the respective section of the memory device; and
the each respective data buffer of the m data buffers is configurable to transmit the respective n-bit-wide section of the data associated with the write operation to the first branch of the respective section of the memory device via the first n-bit-wide write path and not to any memory device in the second branch of the respective section of the memory device via the second n-bit-wide write path.
18 . The memory module of claim 17 , wherein:
the each respective data buffer of the m data buffers further includes input buffers configurable to receive the respective n-bit-wide section of the data associated with the write operation;
selection circuitry coupled to the input buffers; and
logic coupled to the selection circuitry and configurable to control the selection circuitry to select the first n-bit-wide write path to transmit the respective n-bit-wide section of the data associated with the write operation in response to the module control signals.
19 . The memory module of claim 17 , wherein the at least one first memory device includes one or more dynamic random access memory (DRAM) device each having a bit width of n/k, where k is a number of DRAM devices in the at least one first memory device, and k is 1, 2, or 4.
20 . The memory module of claim 19 , wherein n=8 or 16.