Cache optimization for a remote storage device
An apparatus includes a processing device, a network interface configured with a set of channels for communicating data with a target storage unit through a network. The apparatus includes memory, wherein the memory stores computer program instructions that, when executed, cause the processing device to: based on one or more addresses associated with an input/output (I/O) data request, select from the set of channels, a subset of one or more channels from a plurality of subsets of channels having a different associated cache hit probability level, to use to send the I/O data request through a network to a target device having an I/O cache. The processing unit sends, via the network interface, the I/O data request on a channel within the selected subset of one or more channels to access the I/O cache through the network. Associated methods are also disclosed.
1 . A method comprising:
based on one or more addresses associated with an input/output (I/O) data request, selecting from a set of channels by a processing unit, a subset of one or more channels from a plurality of subsets of channels having a different associated cache hit probability level, to use to send the I/O data request through a network to a target device having an I/O cache;
sending, by the processing unit, the I/O data request on a channel within the selected subset of one or more channels to access the I/O cache through the network;
predicting an I/O cache hit probability level for the I/O data request, wherein predicting the I/O cache hit probability level for the I/O data request comprises using a depth level of the address in a request queue and comparing a predicted I/O cache hit probability level to a threshold,
wherein the request queue comprises entries containing corresponding I/O data requests that are to be sent and that have already been processed, and
wherein the entries are assigned hit probability levels based on depth levels of addresses, of the corresponding I/O data requests, in the request queue;
selecting the subset of the one or more channels to communicate the I/O data request to the target device based on the predicted I/O cache hit probability level being within a corresponding defined cache hit probability level for the selected subset of channels; and
dynamically changing a number of channels currently assigned within the subset of the one or more channels based on at least one of a hit rate of addresses communicated by a subset of channels or a miss rate of addresses communicated by a subset of channels.
2 . The method of claim 1 , comprising defining the plurality of subsets of one or more channels from the set of channels for communicating the I/O data request into the different associated cache hit probability level using a defined cache hit probability level for each subset of the plurality of subsets.
3 . The method of claim 1 , comprising dynamically changing the number of channels currently assigned within the subset of the one or more channels based on: an amount of traffic that falls within a threshold associated with each subset of one or more channels, the hit rate of addresses communicated by a subset of channels, and the miss rate of addresses communicated by a subset of channels.
4 . The method of claim 1 , comprising retrieving cached data from an I/O cache in the target device, through the network using the channel.
5 . The method of claim 1 , wherein selecting the subset of one or more channels from the plurality of subsets comprises:
comparing the predicted I/O cache hit probability level of the address of the I/O data request to each threshold representing a different cache hit probability level for each subset of channels; and
routing the I/O data request to the channel in the subset of channels that accommodates the predicted I/O cache hit probability level.
6 . The method of claim 1 , wherein a high cache hit probability level is a range of at least 80% likelihood that the address of the upcoming I/O data request is in the I/O cache.
7 . The method of claim 1 , wherein a medium cache hit probability level is a range of between 50% to 79% likelihood that the address of the upcoming I/O data request is in the I/O cache.
8 . The method of claim 1 , wherein a low cache hit probability level is a range of below 49% likelihood that the address of the upcoming I/O data request is in the I/O cache.
9 . A computer program product comprising a computer readable storage medium, wherein the computer readable storage medium comprises computer program instructions that, when executed:
based on one or more addresses associated with an input/output (I/O) data request, selects from a set of channels, a subset of one or more channels from a plurality of subsets of channels having a different associated cache hit probability level, to use to send the I/O data request through a network to a target device having an I/O cache;
sends the I/O data request on a channel within the selected subset of one or more channels to access the I/O cache through the network;
predicts an I/O cache hit probability level for the I/O data request, wherein predicting the I/O cache hit probability level for the I/O data request comprises using a depth level of the address in a request queue and comparing a predicted I/O cache hit probability level to a threshold,
wherein the request queue comprises entries containing corresponding I/O data requests that at least one of: are to be sent or have already been processed, and
wherein the entries are assigned hit probability levels based on depth levels of addresses, of the corresponding I/O data requests, in the request queue;
selects the subset of the one or more channels to communicate the I/O data request to the target device based on the predicted I/O cache hit probability level being within a corresponding defined cache hit probability level for the selected subset of channels; and
dynamically changes a number of channels currently assigned within the subset of the one or more channels based on at least one of a hit rate of addresses communicated by a subset of channels or a miss rate of addresses communicated by a subset of channels.
10 . The computer program product of claim 9 , wherein the computer readable storage medium comprises computer program instructions that, when executed:
defines the plurality of subsets of one or more channels from the set of channels for communicating the I/O data request into the different associated cache hit probability level using a defined cache hit probability level for each subset of the plurality of subsets.
11 . The computer program product of claim 9 , wherein the computer readable storage medium comprises computer program instructions that, when executed:
changes the number of channels currently assigned within the subset of the one or more channels based on: an amount of traffic that falls within a threshold associated with each subset of one or more channels, the hit rate of addresses, or the miss rate of addresses.
12 . The computer program product of claim 9 , wherein the computer readable storage medium comprises computer program instructions that, when executed:
selects the subset of one or more channels from the plurality of subsets by comparing the predicted I/O cache hit probability level of the address of the I/O data request to each threshold representing a different cache hit probability level for each subset of channels; and
routes the I/O data request to the channel in the subset of channels that accommodates the predicted I/O cache hit probability level.
13 . The computer program product of claim 9 , wherein the computer readable storage medium comprises computer program instructions that, when executed:
retrieves cached data from an I/O cache in the target device, through the network using the channel.
14 . An apparatus comprising:
a processing device;
a network interface configured with a set of channels for communicating data with a target storage unit through a network; and
memory operatively coupled to the processing device, wherein the memory stores computer program instructions that, when executed, cause the processing device to:
based on one or more addresses associated with an input/output (I/O) data request, select from the set of channels, a subset of one or more channels from a plurality of subsets of channels having a different associated cache hit probability level, to use to send the I/O data request through a network to a target device having an I/O cache;
send, via the network interface, the I/O data request on a channel within the selected subset of one or more channels to access the I/O cache through the network;
predict an I/O cache hit probability level for the I/O data request, wherein predicting the I/O cache hit probability level for the I/O data request comprises using a depth level of the address in a request queue and comparing a predicted I/O cache hit probability level to a threshold,
wherein the request queue comprises entries containing corresponding I/O data requests that at least one of: are to be sent or have already been processed, and
wherein the entries are assigned hit probability levels based on depth levels of addresses, of the corresponding I/O data requests, in the request queue;
select the subset of the one or more channels to communicate the I/O data request to the target device based on the predicted I/O cache hit probability level being within a corresponding defined cache hit probability level for the selected subset of channels; and
dynamically change a number of channels currently assigned within the subset of the one or more channels based on at least one of a hit rate of addresses communicated by a subset of channels or a miss rate of addresses communicated by a subset of channels.
15 . The apparatus of claim 14 , wherein the memory stores computer program instructions that, when executed, cause the processing device to:
define the plurality of subsets of one or more channels from the set of channels for communicating the I/O data request into the different associated cache hit probability level using a defined cache hit probability level for each subset of the plurality of subsets.
16 . The apparatus of claim 14 , wherein the memory stores computer program instructions that, when executed, cause the processing device to:
dynamically change the number of channels currently assigned within the subset of the one or more channels based on the hit rate of addresses and the miss rate of addresses,
wherein, to change the number of channels, the processing device is to increase the number of channels by adding one or more channels from an additional subset of channels with cache misses that exceed a miss threshold, and
wherein the one or more channels are added based on cache hits, of the subset of the one or more channels, exceeding a hit threshold.
17 . The apparatus of claim 14 , wherein the memory stores computer program instructions that, when executed, cause the processing device to:
retrieve cached data from an I/O cache in the target device, through the network using the channel.
18 . The apparatus of claim 14 , wherein the memory stores computer program instructions that, when executed, cause the processing device to:
select the subset of one or more channels from the plurality of subsets by comparing the predicted I/O cache hit probability level of the address of the I/O data request to each threshold representing a different cache hit probability level for each subset of channels; and
route the I/O data request to the channel in the subset of channels that accommodates the predicted I/O cache hit probability level.
19 . The apparatus of claim 18 , wherein the memory stores computer program instructions that, when executed, cause the processing device to:
program a threshold corresponding to each different cache hit probability level for each subset of channels that represents a different cache hit probability level for each subset of channels; and
select the subset of one or more channels from the plurality of subsets by comparing the predicted I/O cache hit probability level of the address of the I/O data request to each programmed threshold.
20 . The apparatus of claim 14 , wherein:
a high cache hit probability level is a range of at least 80% likelihood that the address of the upcoming I/O data request is in the I/O cache;
a medium cache hit probability level is a range between 50% to 79% likelihood that the address of the upcoming I/O data request is in the I/O cache; and
a low cache hit probability level is a range below 49% likelihood that the address of the upcoming I/O data request is in the I/O cache.