Cache line invalidation technologies
Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU).
1 . A method comprising:
invalidating multiple cache lines associated with a memory address range in a cache device based on receipt of a command from a device, wherein the command requests reading of data stored in the multiple cache lines and invalidation of the multiple cache lines, wherein the cache device is associated with a processor, wherein the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU), wherein a descriptor includes the command, and wherein the descriptor is to request the device to transmit a packet that includes the data stored in the multiple cache lines that are to be invalidated.
2 . The method of claim 1 , wherein the command is to request evicting the multiple cache lines associated with the memory address range.
3 . The method of claim 1 , wherein the device comprises a network interface device.
4 . The method of claim 1 , comprising: a caching agent (CA) marking the multiple cache lines associated with the memory address range as invalid or evicting data associated with the multiple cache lines based on the command being a permitted request.
5 . An apparatus comprising:
a device to be coupled to a processor by a device interface, wherein the device comprises:
circuitry, wherein the circuitry is to receive a descriptor, wherein the descriptor comprises a command that is to cause the circuitry to read data associated with a memory address range and cause invalidation of multiple cache lines associated with the memory address range in a cache device, wherein the cache device is associated with the processor, wherein the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU), and wherein the descriptor is to request the device to transmit a packet that includes the data stored in the multiple cache lines that are to be invalidated.
6 . The apparatus of claim 5 , wherein the command is to request eviction of the multiple cache lines associated with the memory address range.
7 . The apparatus of claim 5 , wherein the device comprises a network interface device.
8 . The apparatus of claim 5 , wherein the command is provided in a Peripheral Component Interconnect Express (PCIe) consistent transaction layer packet (TLP) Processing Hint (TPH).
9 . The apparatus of claim 5 , wherein the command is to cause a caching agent (CA) to mark the multiple cache lines associated with the memory address range as invalid or evict data associated with the multiple cache lines based on the command being a permitted command.
10 . The apparatus of claim 5 , wherein the command is associated with one or more settings in a descriptor.
11 . The apparatus of claim 5 , wherein the device interface is to perform at least one of: provide communications between the device and the processor on different dies, provide communications between the device and the processor on different chips, provide communications between the device and the processor on different chiplets, provide communications between the device and the processor on different circuit boards, or provide communications between the device and the processor on different packages.
12 . The apparatus of claim 5 , wherein the device comprises one or more of: a network interface device, accelerator, storage device, memory device, graphics processing unit, or audio or sound processing device.
13 . The apparatus of claim 5 , comprising a host system communicatively coupled to the device, wherein the host system comprises the cache device to store data associated with the multiple cache lines.
14 . The apparatus of claim 5 , wherein the invalidation of the multiple cache lines does not cause a writeback of the data in the multiple cache lines to memory.
15 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
execute an operating system (OS) to:
configure circuitry with one or more permitted requesters and
enable invalidation of multiple cache lines of a cache device associated with a memory address range based on a command received from a device that requests a read of data from the multiple cache lines and invalidation of the multiple cache lines and based on the command being provided by a permitted requester among the one or more permitted requesters, wherein the cache device is associated with a processor, wherein the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU), wherein a descriptor includes the command, and wherein the descriptor is to request the device to transmit a packet that includes the data stored in the multiple cache lines that are to be invalidated.
16 . The at least one computer-readable medium of claim 15 , wherein the command is to request a read of data from the memory address range and eviction of multiple cache lines associated with the memory address range.
17 . The at least one computer-readable medium of claim 16 , wherein the request is permitted based on the descriptor being associated with a descriptor ring and invalidation or eviction of multiple cache lines is permitted from one or more descriptors from the descriptor ring.
18 . The at least one computer-readable medium of claim 16 , wherein the device comprises one or more of: a network interface device, accelerator, storage device, memory device, graphics processing unit, or audio or sound processing device.
19 . The at least one computer-readable medium of claim 15 , wherein the device comprises a network interface device, wherein the command is to not cause writeback of the data from the multiple cache lines to memory.
20 . The at least one computer-readable medium of claim 15 , wherein the command is provided in a Peripheral Component Interconnect Express (PCIe) consistent transaction layer packet (TLP) Processing Hint (TPH).
21 . The at least one computer-readable medium of claim 15 , wherein the invalidation of the multiple cache lines is to cause a caching agent (CA) to mark the multiple cache lines associated with the memory address range as invalid or evict data associated with the multiple cache lines based on the command being associated with the permitted requester.