Event-based debug, trace, and profile in device with data processing engine array
A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.
1 . A die comprising:
an array of data processing engines (DPEs), each of the DPEs comprising:
a core;
a memory module;
event logic configured to detect an occurrence of one or more events in the core or the memory module, wherein the event logic comprises stall logic configured for operations selected from the group comprising: halting execution of the core, resuming execution of the core, setting breakpoints, and synchronizing a timer based on writable configuration registers and the one or more events detected by the event logic;
an event broadcast circuitry coupled to the event logic and configured to receive an indication of a detected event detected by the event logic; and
an event broadcast network comprising interconnections between the event broadcast circuitry of the DPEs, wherein the event broadcast circuitry is configured to send, using the event broadcast network, a respective indication for each of the one or more events after the one or more events occurred to the DPEs, and wherein the respective indication informs the DPEs that the event logic detected the occurrence of one of the one or more events.
2 . The die of claim 1 , wherein, for each of the DPEs, the event broadcast circuitry is configurable, based on the writable configuration registers, to identify which ones of a plurality of detected events that the event broadcast circuitry is configurable to receive are to be broadcast in the event broadcast network upon receipt of the ones of the plurality of detected events from the event broadcast circuitry.
3 . The die of claim 1 , wherein, for each of the DPEs, the event broadcast circuitry is configurable, based on the writable configuration registers, to selectively broadcast a received indication of the detected event in one or more distinct directions based on which of the one or more distinct directions the received indication was received from the event broadcast network.
4 . The die of claim 1 , wherein, for each of the DPEs, the event logic is configurable to monitor conditions of the core or the memory module which indicate whether the one or more events have occurred.
5 . The die of claim 1 , wherein, for each of the DPEs:
the event logic includes:
first event logic in the core, the first event logic being configured to detect a second occurrence of a second one or more events in the core; and
second event logic in the memory module, the second event logic being configured to detect a third occurrence of a third one or more events in the memory module;
the event broadcast circuitry includes:
a first event broadcast circuitry connected to the first event logic and configurable to receive a second indication of a second detected event detected by the first event logic; and
a second event broadcast circuitry connected to the second event logic and configurable to receive a third indication of a third detected event detected by the second event logic;
the first event broadcast circuitry is connected to the second event broadcast circuitry;
when a respective DPE of the DPEs has a first neighboring DPE above the respective DPE in the array, the first event broadcast circuitry of the respective DPE is connected to the first event broadcast circuitry of the first neighboring DPE, and the second event broadcast circuitry of the respective DPE is connected to the second event broadcast circuitry of the first neighboring DPE;
when the respective DPE has a second neighboring DPE below the respective DPE in the array, the first event broadcast circuitry of the respective DPE is connected to the first event broadcast circuitry of the second neighboring DPE, and the second event broadcast circuitry of the respective DPE is connected to the second event broadcast circuitry of the second neighboring DPE;
when the respective DPE has a third neighboring DPE disposed laterally next to the respective DPE in the array, one of the first event broadcast circuitry or the second event broadcast circuitry of the respective DPE is connected to one of the first event broadcast circuitry or the second event broadcast circuitry of the third neighboring DPE; and
when the respective DPE has a fourth neighboring DPE disposed laterally next to the respective DPE and opposite from the third neighboring DPE in the array, the other one of the first event broadcast circuitry or the second event broadcast circuitry of the respective DPE is connected to one of the first event broadcast circuitry or the second event broadcast circuitry of the fourth neighboring DPE.
6 . The die of claim 1 , wherein each of the DPEs further comprises response logic coupled to the event logic, the response logic being configurable by the writable configuration registers, the response logic being operable to trigger a response based upon the writable configuration registers and one or more detected events detected by the event logic.
7 . The die of claim 6 , wherein, for each of the DPEs, the response logic comprises trace hardware operable to capture trace data based on the writable configuration registers and the one or more detected events detected by the event logic.
8 . The die of claim 6 , wherein, for each of the DPEs, the response logic comprises performance counter hardware operable to operate one or more performance counters based on the writable configuration registers and the one or more detected events detected by the event logic.
9 . A method for operating a die, the method comprising:
operating a plurality of data processing engines (DPEs) of an array of DPEs on the die, each of the plurality of DPEs comprising a core and a memory module;
during operation of a first DPE of the plurality of DPEs, detecting an event in the core or the memory module of the first DPE by event logic in the first DPE, wherein the event logic comprises stall logic configured for operations selected from the group comprising: halting execution of the core, resuming execution of the core, setting breakpoints, and synchronizing a timer based on writable configuration registers and the event detected by the event logic; and
in response to detecting the event, broadcasting an indication of the detected event from the first DPE to at least two of the plurality of DPEs via an event broadcast network, the event broadcast network comprising interconnected event broadcast circuitry of the plurality of DPEs.
10 . The method of claim 9 , wherein the event logic is configured to detect the event based on data written to the writable configuration registers.
11 . The method of claim 9 , wherein the interconnected event broadcast circuitry are each configured to propagate signals based on data written to the writable configuration registers.
12 . The method of claim 9 , wherein each of the DPEs in the array of DPEs includes a first event broadcast circuitry and a second event broadcast circuitry in the respective DPE, wherein the interconnected event broadcast circuitry include, for each of the DPEs in the array of DPEs:
the first event broadcast circuitry of the respective DPE is connected to the second event broadcast circuitry of the respective DPE;
when a respective DPE of the DPEs has a first neighboring DPE above the respective DPE in the array, the first event broadcast circuitry of the respective DPE is connected to the first event broadcast circuitry of the first neighboring DPE, and the second event broadcast circuitry of the respective DPE is connected to the second event broadcast circuitry of the first neighboring DPE;
when the respective DPE has a second neighboring DPE below the respective DPE in the array, the first event broadcast circuitry of the respective DPE is connected to the first event broadcast circuitry of the second neighboring DPE, and the second event broadcast circuitry of the respective DPE is connected to the second event broadcast circuitry of the second neighboring DPE;
when the respective DPE has a third neighboring DPE disposed laterally next to the respective DPE in the array, one of the first event broadcast circuitry or the second event broadcast circuitry of the respective DPE is connected to one of the first event broadcast circuitry or the second event broadcast circuitry of the third neighboring DPE; and
when the respective DPE has a fourth neighboring DPE disposed laterally next to the respective DPE and opposite from the third neighboring DPE in the array, the other one of the first event broadcast circuitry or the second event broadcast circuitry of the respective DPE is connected to one of the first event broadcast circuitry or the second event broadcast circuitry of the fourth neighboring DPE.
13 . The method of claim 9 , further comprising triggering a response by response logic of at least one of the first DPE or one of the plurality of DPEs based upon the detected event.
14 . The method of claim 13 , wherein the response is performing a debugging operation, a tracing operation, a profiling operation, or a combination thereof.
15 . A device comprising:
an array of data processing engines (DPEs) on a die, each of the DPEs comprising:
a core;
a memory module;
core event logic in the core, the core event logic being configured to detect an occurrence of a first one or more events in the core, wherein the core event logic comprises stall logic configured for operations selected from the group comprising: halting execution of the core, resuming execution of the core, setting breakpoints, and synchronizing a timer based on writable core configuration registers and the first one or more events detected by the core event logic;
memory event logic in the memory module, the memory event logic being configured to detect an occurrence of a second one or more events in the memory module;
a first event broadcast circuitry connected to the core event logic, the first event broadcast circuitry being configurable to propagate a first received signal selectively in a first one or more predefined directions, wherein the first received signal is a respective indication for each of the first one or more events after the first one or more events occurred; and
a second event broadcast circuitry connected to the memory event logic, the first event broadcast circuitry being connected to the second event broadcast circuitry, the second event broadcast circuitry being configurable to propagate a second received signal selectively in a second one or more predefined directions, wherein the second received signal is a respective indication for each of the second one or more events after the second one or more events occurred, and
wherein the first event broadcast circuitry and the second event broadcast circuitry of the DPEs are interconnected to form an event broadcast network, and wherein the first event broadcast circuitry and the second event broadcast circuitry uses the event broadcast network to propagate the first received signal and the second received signal.
16 . The device of claim 15 further comprising a system interface block comprising a plurality of tiles, each of the plurality of tiles being connected to and configured to operate as an interface for a column of DPEs of the array of DPEs, the system interface block being connected to the event broadcast network.
17 . The device of claim 16 further comprising:
a system network connected to the system interface block;
programmable logic connected to the system network and to the system interface block, wherein the event broadcast network and the system interface block are configurable to transmit an indication of an event detected by at least one of the core event logic or the memory event logic of the DPEs to the programmable logic; and
a processing system connected to the system network.
18 . The device of claim 15 , wherein each of the DPEs further comprises:
first trace hardware coupled to the core event logic and configurable to capture core trace data upon receipt of an indication of a detected event from the core event logic; and
first performance counter hardware coupled to the core event logic and configurable to control a core performance counter upon receipt of the indication of the detected event from the core event logic.
19 . The device of claim 18 , wherein each of the DPEs further comprises:
second trace hardware coupled to the memory event logic and configurable to capture memory trace data upon receipt of a second indication of a second detected event from the memory event logic; and
second performance counter hardware coupled to the memory event logic and configurable to control a memory performance counter upon receipt of the second indication of the detected event from the memory event logic.