Unblock request

1 . An unblock-request-transmitting interconnect circuit node, comprising:

transmitting interface circuitry configured to transmit outgoing requests based on one or more incoming requests received from at least one request source, each outgoing request specifying a target node to which that outgoing request is to be transmitted; and

control circuitry configured to control the transmitting interface circuitry; in which:

in response to at least one incoming write request received from a strong-order-requiring request source requiring transmission of a set of strongly ordered write push requests subject to an ordering requirement preventing a younger request from being observed as completing before an older request, each write push request specifying write target data and write target address information for identifying one or more addressed locations to which the write target data is to be written, and the set of strongly ordered write push requests comprising at least a first write push request which specifies a first target node and a second write push request which is younger than the first write push request and specifies a second target node, the control circuitry is configured to control the transmitting interface circuitry to:

transmit the first write push request specifying the first target node;

prior to a completion response being received from the first target node for the first write push request, transmit the second write push request specifying the second target node; and

in response to the completion response being received from the first target node for the first write push request, transmit an unblock request specifying the second target node, the unblock request indicating that an unblocking condition is allowed to become satisfied for the second write push request enabling the second target node or a further node downstream of the second target node to release a block on completion of a conflicting read request which requests a read to one of said one or more addressed locations identified by the write target address information specified by the second write push request.

2 . The unblock-request-transmitting interconnect circuit node according to claim 1 , in which a given write push request of the set of strongly ordered write push requests specifies unblock type information indicative of whether the give write push request is an explicit unblock type of write push request for which the unblock request is required to be transmitted to enable the unblocking condition to be satisfied for the explicit unblock type of write push request, or an implicit unblock type of write push request for which the unblocking condition is allowed to be satisfied even if no unblock request has been transmitted for the implicit unblock type of write push request.

3 . The unblock-request-transmitting interconnect circuit node according to claim 2 , in which the control circuitry is configured to control the transmitting interface circuitry to:

transmit the given write push request as the explicit unblock type of write push request, when the given write push request is not an initial write push request of the set of strongly ordered write push requests and specifies a different target node to a target node specified for a preceding write push request of the set of strongly ordered write push requests; and

transmit the given write push request as the implicit unblock type for the given write push request, when the given strongly ordered write push request is the initial write push request or specifies a same target node as the preceding strongly ordered write push request of the set.

4 . The unblock-request-transmitting interconnect circuit node according to claim 1 , in which the transmitting interface circuitry is configured to transmit the set of strongly ordered write push requests on a communication channel which provides a guarantee that a set of strongly ordered write push requests corresponding to a first strong-order-requiring request source cannot cause blocking of a set of strongly ordered write push requests corresponding to a second strong-order-requiring request source.

5 . The unblock-request-transmitting interconnect circuit node according to claim 4 , in which the transmitting interface circuitry is configured to allocate the set of strongly ordered write push requests corresponding to the first strong-order-requiring request source to a first resource plane different from a second resource plane allocated for handling the set of strongly ordered write push requests corresponding to the second strong-order-requiring request source, the first resource plane and second resource plane providing separate hardware resources for communication of requests on the communication channel.

6 . The unblock-request-transmitting interconnect circuit node according to claim 4 , in which the communication channel comprises shared hardware resource shared between the set of strongly ordered write push requests corresponding to the first strong-order-requiring request and the set of strongly ordered write push requests corresponding to the second strong-order-requiring request source; and

the transmitting interface circuitry is configured to manage transmission of the set of strongly ordered write push requests corresponding to the first strong-order-requiring request source based on availability of a first type of credit different to a second type of credit used to manage transmission of the set of strongly ordered write push requests corresponding to the second strong-order-requiring request source.

7 . The unblock-request-transmitting interconnect circuit node according to claim 1 , in which the strong-order-requiring request source comprises a PCIe source configured to generate the incoming requests based on PCIe transactions received on a PCIe communications link.

8 . The unblock-request-transmitting interconnect circuit node according to claim 1 , in which the unblock-request-transmitting interconnect circuit node comprises an ingress interface for an interconnect, the ingress interface comprising protocol conversion circuitry configured to convert between incoming requests defined according to an upstream protocol used by the at least one request source and the outgoing requests defined according to an interconnect transport protocol used by the interconnect.

9 . An unblock-request-receiving interconnect circuit node, comprising:

receiving interface circuitry configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written; and

read blocking control circuitry configured to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the receiving interface circuitry.

10 . The unblock-request-receiving interconnect circuit node according to claim 9 , in which the read blocking control circuitry comprises tracking circuitry configured to maintain one or more tracking entries, each tracking entry configured to track address information corresponding to a given write push request for which the unblocking condition is not yet satisfied; and

in response to a given read request received at the receiving interface circuitry, the read blocking control circuitry is configured to determine whether to block completion of the given read request based on a lookup of read target address information of the given read request in the tracking circuitry to determine whether the read target address information corresponds to the address information tracked by a tracking entry for a write push request for which the unblocking condition is not yet satisfied.

11 . The unblock-request-receiving interconnect circuit node according to claim 10 , in which the given write push request specifies a request source identifier identifying a request source which caused the given write push request to be transmitted to the receiving interface circuitry; and

the tracking circuitry is configured to reserve at least one dedicated tracking entry per strong-order-requiring request source, each strong-order-requiring request source comprising a request source capable of causing a transmission of a set of strongly ordered write push requests which are subject to an ordering requirement preventing a younger request from being observed as completing before an older request.

12 . The unblock-request-receiving interconnect circuit node according to claim 9 , in which the read blocking control circuitry is configured to enforce the requirement for the conflicting read request by delaying a timing of transmitting a write completion acknowledgement for the write push request to a downstream circuit node until the unblocking condition is satisfied for the write push request, the write completion acknowledgement indicating that the downstream circuit node is allowed to release a block on completion of the conflicting read request.

13 . The unblock-request-receiving interconnect circuit node according to claim 9 , in which the given write push request specifies unblock type information indicative of whether the give write push request is an explicit unblock type of write push request for which the unblock request is required to be received to enable the unblocking condition to be satisfied for the explicit unblock type of write push request, or an implicit unblock type of write push request for which the unblocking condition is allowed to be satisfied even if no unblock request has been received for the implicit unblock type of write push request.

14 . The unblock-request-receiving interconnect circuit node according to claim 13 , in which, when the given write push request is the explicit unblock type of write push request, satisfaction of the unblocking condition is dependent on each of the following conditions being satisfied:

the unblock request has been received for the given write push request;

a write completion response has been received for the given write push request; and

the unblocking condition is satisfied for any older write push request of a set of strongly ordered write push requests comprising the given write push request.

15 . The unblock-request-receiving interconnect circuit node according to claim 13 , in which, when the given write push request is the implicit unblock type of write push request, satisfaction of the unblocking condition is dependent on each of the following conditions being satisfied, independent of whether any unblock request has been received for the given write push request:

a write completion response has been received for the given write push request; and

when the given write push request is one of a set of strongly ordered write push requests, the unblocking condition is satisfied for any older write push request of the set of strongly ordered write push requests.

16 . The unblock-request-receiving interconnect circuit node according to claim 9 , in which the unblock-request-receiving interconnect circuit node comprises an egress interface for an interconnect, the egress interface comprising protocol conversion circuitry configured to convert between incoming requests defined according to an interconnect transport protocol used by the interconnect and outgoing requests defined according to a downstream protocol used by a downstream circuit node.

17 . An interconnect circuit comprising:

an unblock-request-receiving interconnect circuit node configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written, and to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the unblock-request-receiving interconnect circuit node; and

an unblock-request-transmitting interconnect circuit node configured to transmit the given write push request to the unblock-request-receiving interconnect circuit node, and to transmit the unblock request for the given write push request in response to receipt of a completion response for an older write push request transmitted by the unblock-request-transmitting interconnect circuit node.

18 . A system comprising:

the interconnect circuit according to claim 17 , implemented in at least one packaged chip;

at least one system component; and

a board,

wherein the at least one packaged chip and the at least one system component are assembled on the board.

19 . A chip-containing product comprising the system of claim 18 , wherein the system is assembled on a further board with at least one other product component.

20 . A non-transitory computer-readable medium storing computer-readable code for fabrication of the unblock-request-transmitting interconnect circuit node of claim 1 .