Heterogeneous accelerator for highly efficient learning systems
An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.
1 . An apparatus, comprising:
a first processing unit;
a second processing unit;
a third processing unit;
system memory; and
a high bandwidth memory (HBM) stack;
wherein the first processing unit is configured to assign a first portion of a task to the second processing unit and a second portion of the task to the third processing unit;
wherein the second processing unit writes data to the system memory based on performing the first portion of the task;
wherein a triggering event is initiated to inform the third processing unit that the data has been written to the system memory by the second processing unit;
wherein the data is written from the system memory to the HBM stack and the third processing unit processes the second portion of the task, using the data written to the HBM stack based on the triggering event.
2 . The apparatus of claim 1 , wherein processing the second portion of the task comprises executing the second portion of the task based on the triggering event.
3 . The apparatus of claim 2 , wherein the second processing unit is configured to asynchronously execute a second task.
4 . The apparatus of claim 1 , wherein the first processing unit is configured to assign the second processing unit the first portion of the task and the third processing unit the second portion of the task based on availability of the first second processing unit and the third processing unit.
5 . The apparatus of claim 1 , wherein the first portion of the task comprises controlling processing-in-memory functionality of the HBM stack.
6 . The apparatus of claim 1 , wherein the second processing unit is configured to access the system memory via remote direct memory access (RDMA).
7 . The apparatus of claim 1 , wherein the third processing unit comprises a polling circuit to detect when the triggering event occurs.
8 . The apparatus of claim 7 , wherein the second processing unit is configured to copy data from the system memory to the HBM stack.
9 . The apparatus of claim 8 , wherein the third processing unit is configured to copy data from the system memory via remote direct memory access (RDMA).
10 . A system, comprising:
a first processing unit;
a second processing unit;
a third processing unit, wherein the first processing unit is configured to assign the second processing unit a first task and the third processing unit a second task;
a High Bandwidth Memory (HBM) stack; and
system memory, wherein the second processing unit is configured to write data for the first task to the system memory, and the first processing unit is further configured to initiate a triggering event indicating that the second processing unit has written data to the system memory;
wherein the data is copied from the system memory to the HBM stack and the third processing unit processes the second task, using the data written to the HBM stack, based on the triggering event.
11 . The system of claim 10 , wherein processing the second task comprises executing the second task based on the triggering event.
12 . The system of claim 10 , wherein the third processing unit is configured to execute the second task, wherein the second task comprises controlling processing-in-memory functionality of HBM dies of the HBM stack.
13 . The system of claim 10 , wherein the first processing unit, the second processing unit, and the third processing unit are coupled using a Peripheral Component Interconnect Express (PCIe) protocol.
14 . An apparatus, comprising:
a first processing unit;
a second processing unit;
a third processing unit;
system memory; and
a High Bandwidth Memory (HBM) stack;
wherein the second processing unit is assigned a first task and the third processing unit is assigned a second task from the first processing unit;
wherein the second processing unit writes data for the first task to cache memory; wherein the second processing unit writes the data from the cache memory to the system memory;
wherein the data is written from the system memory to the HBM stack; and
wherein the second processing unit executes the second task using the data in the HBM stack based on the data being written from the system memory to the HBM stack.
15 . The apparatus of claim 14 , wherein the third processing unit is configured to execute the second task based on a triggering indication.
16 . The apparatus of claim 14 , wherein the second processing unit is configured to asynchronously execute a third task based on a triggering indication.
17 . The apparatus of claim 14 , wherein the first processing unit assigns the second processing unit the first task and the third processing unit the second task based on availability of the second processing unit and the third processing unit.
18 . The apparatus of claim 14 , wherein the first task comprises controlling processing-in-memory functionality of the HBM stack.
19 . The apparatus of claim 14 , wherein the third processing unit comprises a polling circuit to detect when a triggering indication occurs.
20 . The apparatus of claim 14 , wherein the third processing unit is configured to copy data from the system memory via remote direct memory access (RDMA).