Computing-in-memory circuit, chip and electronic device

1 . A computing-in-memory circuit, comprises a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit;

the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2;

the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on N-way currents output from the N resistive random access memories selected;

the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

2 . The computing-in-memory circuit according to claim 1 , wherein the resistive random access memory array comprises source line, word line, bit line and a plurality of memory units, one memory unit comprises one first transistor and one resistive random access memory;

the source of the first transistor is connected to the source line, the gate thereof is connected to the word line;

the resistive random access memory is connected between the drain of the first transistor and the clamping circuit.

3 . The computing-in-memory circuit according to claim 2 , wherein the number of the clamping circuit is equal to the number of the memory unit; one clamping circuit is connected between the signal input terminal and one memory unit;

the clamping circuit comprises an operational amplifier and a second transistor; the positive input terminal of the operational amplifier is connected to the signal input terminal, the inverting input terminal thereof is connected to the bit line, and the output terminal thereof is connected to the gate of the second transistor; the source of the second transistor is connected to the bit line, the drain thereof is connected to the current mirror.

4 . The computing-in-memory circuit according to claim 1 , wherein the analog-to-digital conversion circuit is a current-type successive approximation analog-to-digital conversion circuit.

5 . The computing-in-memory circuit according to claim 4 , wherein the current-type successive approximation analog-to-digital conversion circuit comprises: a third transistor, a fourth transistor, a first inverter, a second inverter and a third inverter;

the drain of the third transistor is connected to the reference current array, the source thereof is connected to the source of the fourth transistor, the gate thereof is connected to the gate of the fourth transistor; the drain of the fourth transistor is connected to the current mirror;

the output terminal of the first inverter and the input terminal of the second inverter are connected to the drain of the fourth transistor; the input terminal of the first inverter and the output terminal of the second inverter are connected to the input terminal of the third inverter.

6 . The computing-in-memory circuit according to claim 5 , wherein the first inverter comprises a first pull-up transistor and a first pull-down transistor, the second inverter comprises a second pull-up transistor and a second pull-down transistor, the third inverter comprises a third pull-up transistor and a third pull-down transistor;

the drain of the first pull-up transistor, the source of the second pull-up transistor and the source of the third pull-up transistor are connected to the power supply; the drain of the first pull-down transistor, the source of the second pull-down transistor and the source of the third pull-down transistor are grounded;

the source of the first pull-up transistor is connected to the source of the first pull-down transistor, the gate of the first pull-up transistor is connected to the gate of the first pull-down transistor;

the gate of the second pull-up transistor is connected to the gate of the second pull-down transistor, the drain of the second pull-up transistor is connected to the drain of the second pull-down transistor;

the gate of the third pull-up transistor is connected to the gate of the third pull-down transistor, the drain of the third pull-up transistor is connected to the drain of the third pull-down transistor.

7 . The computing-in-memory circuit according to claim 5 , further comprising a digital combined circuit, wherein the input terminal of the digital combined circuit is connected to the output terminal of the third inverter, configured to convert the digital signal to a target encoding.

8 . The computing-in-memory circuit according to claim 1 , further comprising an address decoder, wherein the address decoder is connected between the signal input terminal and the resistive random access memory array.

9 . A computing-in-memory chip, comprising a computing-in-memory circuit, the computing-in-memory circuit, comprises a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit;

the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to N resistive random access memories selected of the resistive random access memory array, wherein Nis an integer and N≥2;

the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on N-way currents output from the N resistive random access memories selected;

the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

10 . An electronic device, comprising the computing-in-memory chip according to claim 9 .

11 . The computing-in-memory chip according to claim 9 , wherein the resistive random access memory array comprises source line, word line, bit line and a plurality of memory units, one memory unit comprises one first transistor and one resistive random access memory;

the source of the first transistor is connected to the source line, the gate thereof is connected to the word line;

the resistive random access memory is connected between the drain of the first transistor and the clamping circuit.

12 . The computing-in-memory chip according to claim 10 , wherein the number of the clamping circuit is equal to the number of the memory unit; one clamping circuit is connected between the signal input terminal and one memory unit;

the clamping circuit comprises an operational amplifier and a second transistor; the positive input terminal of the operational amplifier is connected to the signal input terminal, the inverting input terminal thereof is connected to the bit line, and the output terminal thereof is connected to the gate of the second transistor; the source of the second transistor is connected to the bit line, the drain thereof is connected to the current mirror.

13 . The computing-in-memory chip according to claim 9 , wherein the analog-to-digital conversion circuit is a current-type successive approximation analog-to-digital conversion circuit.

14 . The computing-in-memory chip according to claim 12 , wherein the current-type successive approximation analog-to-digital conversion circuit comprises: a third transistor, a fourth transistor, a first inverter, a second inverter and a third inverter;

the drain of the third transistor is connected to the reference current array, the source thereof is connected to the source of the fourth transistor, the gate thereof is connected to the gate of the fourth transistor; the drain of the fourth transistor is connected to the current mirror;

the output terminal of the first inverter and the input terminal of the second inverter are connected to the drain of the fourth transistor; the input terminal of the first inverter and the output terminal of the second inverter are connected to the input terminal of the third inverter.

15 . The computing-in-memory chip according to claim 13 , wherein the first inverter comprises a first pull-up transistor and a first pull-down transistor, the second inverter comprises a second pull-up transistor and a second pull-down transistor, the third inverter comprises a third pull-up transistor and a third pull-down transistor;

the drain of the first pull-up transistor, the source of the second pull-up transistor and the source of the third pull-up transistor are connected to the power supply; the drain of the first pull-down transistor, the source of the second pull-down transistor and the source of the third pull-down transistor are grounded;

the source of the first pull-up transistor is connected to the source of the first pull-down transistor, the gate of the first pull-up transistor is connected to the gate of the first pull-down transistor;

the gate of the second pull-up transistor is connected to the gate of the second pull-down transistor, the drain of the second pull-up transistor is connected to the drain of the second pull-down transistor;

the gate of the third pull-up transistor is connected to the gate of the third pull-down transistor, the drain of the third pull-up transistor is connected to the drain of the third pull-down transistor.

16 . The computing-in-memory chip according to claim 13 , further comprising a digital combined circuit, wherein the input terminal of the digital combined circuit is connected to the output terminal of the third inverter, configured to convert the digital signal to a target encoding.

17 . The computing-in-memory chip according to claim 9 , further comprising an address decoder, wherein the address decoder is connected between the signal input terminal and the resistive random access memory array.