Clocking a systolic array on both edges of a clock signal

1 . An apparatus, comprising:

a systolic array comprising an initial systolic stage clocked at a first edge of a clock signal, the systolic array further comprising a plurality of additional systolic stages; and

control logic configured to clock a first subset of the plurality of additional systolic stages at the first edge of the clock signal and a second subset of the plurality of additional systolic stages at a second edge of the clock signal, the second edge being different from the first edge,

wherein the initial systolic stage and each of the plurality of additional systolic stages comprise a plurality of processing elements, wherein each respective processing element of the plurality of processing elements includes a multiplier and an accumulator, and

wherein the control logic comprises:

a first plurality of clock delay elements, each of the first plurality of clock delay elements configured to delay the clock signal an entire clock cycle, each of the first plurality of clock delay elements coupled to an input of a respective systolic stage of the plurality of additional systolic stages.

2 . The apparatus of claim 1 , wherein the control logic further comprises:

a first plurality of additional clock delay elements, each of the first plurality of additional clock cycle elements configured to delay the clock signal by a portion of the clock cycle, each of the first plurality of additional clock cycle elements coupled between a respective clock delay element of the first plurality of clock delay elements and the input of the respective systolic stage of the second subset of the plurality of additional systolic stages; and

a second plurality of additional clock delay elements, each of the second plurality of additional clock cycle elements configured to delay the clock signal by a portion of the clock cycle, each of the second plurality of additional clock delay elements coupled to an output of the respective systolic stage of the second subset of the plurality of additional systolic stages.

3 . The apparatus of claim 2 , wherein:

each of the first plurality of additional clock delay elements is configured to trigger on the second edge of the clock signal; and

each of the second plurality of additional clock delay elements is configured to trigger on the first edge of the clock signal.

4 . The apparatus of claim 2 , wherein:

each clock delay element included in the first plurality of clock delay elements comprises a first register triggered at the first edge of the clock signal; and

each clock delay element included in the first plurality of additional clock delay elements comprises a second register triggered at the second edge of the clock signal.

5 . The apparatus of claim 2 , wherein:

each clock delay element included in the first plurality of clock delay elements comprises a register; and

each clock delay element included in the first plurality of additional clock delay elements comprises a latch.

6 . The apparatus of claim 2 , further comprising:

a plurality of multiplexers, each of the plurality of multiplexers coupled between the output of the respective systolic stage of the plurality of additional systolic stages and a respective clock delay element included in the second plurality of additional clock delay elements.

7 . The apparatus of claim 2 , further comprising:

a second plurality of clock delay elements coupled to an output of the initial systolic stage; and

a third plurality of clock delay elements coupled to a respective clock delay element included in the second plurality of additional clock delay elements.

8 . The apparatus of claim 7 , wherein a total number of clock delay elements included in the third plurality of clock delay elements is greater than a total number of clock delays included in the third plurality of clock delay elements.

9 . The apparatus of claim 1 , wherein the first edge comprises a rising edge of the clock signal and the second edge comprises a falling edge of the clock signal.

10 . A method of operating a systolic array, comprising:

clocking a first systolic stage of the systolic array at a first edge of a first cycle of a clock signal; and

clocking a second systolic stage of the systolic array at a second edge of a second cycle of the clock signal that follows the first cycle of the clock signal,

wherein clocking the second systolic stage of the systolic array at the second edge of the second cycle of the clock signal comprises:

delaying the clock signal for a portion of the second cycle; and

in response to the delaying, clocking the second systolic stage of the systolic array at the second edge of the second cycle of the clock signal.

11 . The method of claim 10 , further comprising:

in response to clocking the second systolic stage of the systolic array, delaying the clock signal for the portion of the clock cycle.

12 . The method of claim 10 , wherein the first systolic stage and the second systolic stage each comprise a plurality of processing elements.

13 . The method of claim 12 , wherein each respective processing element of the plurality of processing elements comprises a multiplier and an accumulator.

14 . The method of claim 10 , wherein the first edge comprises a rising edge and the second edge comprises a falling edge.

15 . The method of claim 10 , further comprising:

clocking a third systolic stage of the systolic array at the first edge of a third cycle of the clock signal that follows the second cycle of the clock signal.

16 . An apparatus, comprising:

means for clocking a first systolic stage of a systolic array at a first edge of a first cycle of a clock signal; and

means for clocking a second systolic stage of the systolic array at a second edge of a second cycle of the clock signal,

wherein means for clocking the second systolic stage of the systolic array at the second edge of the second cycle of the clock signal comprises:

means for delaying the clock signal for a portion of the second cycle; and

in response to the delaying, clocking the second systolic stage of the systolic array at the second edge of the second cycle of the clock signal.

17 . The apparatus of claim 16 , wherein the first systolic stage and the second systolic stage each comprise a plurality of processing elements, and wherein each of the plurality of processing elements comprises a multiplier and an accumulator.