IP Library Granted Patent US 12675571
Granted Patent B2
US 12675571 · App. 18/618,861 · Granted Jul 7, 2026

Guard rows to protect regions of memory

Inventors: Shivam Swami (Ottawa, CA); SeyedMohammad SeyedzadehDelcheh (Sammamish, WA)
Assignees: Advanced Micro Devices, Inc; ATI Technologies ULC
G06F21/566G06F2221/034
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Quick Facts
Patent No.
US 12675571
App. No.
18/618,861
Granted
Jul 7, 2026
Kind
B2
Abstract

Multiple guard rows are included in a region of memory. Accesses to the region of memory are monitored and a revolver technique using the guard rows is enabled in response to the number of accesses to the region of memory equaling or exceeding a threshold amount within a given interval of time. The guard rows are moved around the region of memory with one or more non-guard rows being situated between the guard rows. A guard row refers to a row of the region of memory that stores invalid data, whereas the one or more non-guard rows store valid data. After being moved, accesses to the region of memory are monitored and after another threshold number of accesses to the region of memory the guard rows are moved again. This process continues with the guard rows being moved, e.g., in a circular manner, through the region of memory.

Claims (36)

1 . A system comprising:

a physical memory; and

a memory controller configured to:

monitor accesses to a region of the physical memory; and

move multiple guard rows through the region of memory in response to a number of accesses to the region satisfying a first threshold, wherein a pivot row is located between at least a first guard row of the multiple guard rows and a second guard row of the multiple guard rows, and wherein the pivot row stores valid data and each of the multiple guard rows stores invalid data.

2 . The system of claim 1 , wherein the memory controller is configured to:

receive a system physical address corresponding to an access to the region;

generate a logical row address from the system physical address;

map the logical row address to a physical row address; and

perform the access to the region using the physical row address.

3 . The system of claim 1 , wherein each of the accesses comprises activation of a row of the region.

4 . The system of claim 1 , wherein the region comprises a subarray.

5 . The system of claim 1 , wherein the first guard row is in a first row adjacent to the pivot row.

6 . The system of claim 5 , wherein the second guard row is in a second row adjacent to the pivot row.

7 . The system of claim 1 , wherein the memory controller is configured to repeatedly move, after the number of accesses to the region since the multiple guard rows were previously moved satisfies a second threshold, the multiple guard rows.

8 . The system of claim 7 , wherein the memory controller is configured to not move the multiple guard rows in response to all of the accesses to the region since the multiple guard rows were previously moved being to the pivot row.

9 . A memory controller configured to:

monitor accesses to a region of physical memory and enable guard row movement in response to a number of accesses to the region satisfying a first threshold; and

in response to the guard row movement being enabled, move multiple guard rows through the region, wherein a pivot row is located between at least a first guard row of the multiple guard rows and a second guard row of the multiple guard rows, and wherein the pivot row stores valid data and each of the multiple guard rows stores invalid data.

10 . The memory controller of claim 9 , wherein the region comprises a subarray, and each of the accesses comprises activation of a row of the subarray, and wherein the first guard row is in a first row adjacent to the pivot row and the second guard row is in a second row adjacent to the pivot row.

11 . The memory controller of claim 9 , wherein the memory controller is configured to repeatedly move, after the number of accesses to the region since the multiple guard rows were previously moved satisfies a second threshold, the multiple guard rows.

12 . The memory controller of claim 11 , wherein the memory controller is configured to not move the multiple guard rows in response to all of the accesses to the region since the multiple guard rows were previously moved being to the pivot row.

13 . A method comprising:

monitoring accesses to a region; and

moving multiple guard rows through the region in response to a number of accesses to the region satisfying a first threshold, wherein a pivot row is located between at least a first guard row of the multiple guard rows and a second guard row of the multiple guard rows, and wherein the pivot row stores valid data and each of the multiple guard rows stores invalid data.

14 . The method of claim 13 , further comprising:

receiving a system physical address corresponding to an access to the region of memory;

generating a logical row address from the system physical address;

mapping the logical row address to a physical row address; and

performing the access to the region of memory using the physical row address.

15 . The method of claim 13 , wherein each of the accesses comprises activation of a row of the region of memory.

16 . The method of claim 13 , wherein the region of memory comprises a subarray.

17 . The method of claim 13 , wherein the first guard row is in a first row adjacent to the pivot row.

18 . The method of claim 17 , wherein the second guard row is in a second row adjacent to the pivot row.

19 . The method of claim 13 , further comprising repeatedly moving, after the number of accesses to the region of memory since the multiple guard rows were previously moved satisfies a second threshold, the multiple guard rows.

20 . The method of claim 19 , further comprising not moving the multiple guard rows in response to all of the accesses to the region of memory since the multiple guard rows were previously moved being to the pivot row.