IP Library › Granted Patent US 12675622
Granted Patent B1
US 12675622 · App. 18/302,687 · Granted Jul 7, 2026

Signoff-safe multi-corner reduction for static timing analysis

Inventors: Brian D. Clerkin (Lusk, IE); Subramanyam Sripada (Hillsboro, OR); Praveen Ghanta (Palo Alto, CA); Peivand Tehrani (Camarillo, CA); Xihui Li (Dublin, IE)
Assignee: SYNOPSYS, INC.
G06F30/3312G06F2119/12
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Quick Facts
Patent No.
US 12675622
App. No.
18/302,687
Granted
Jul 7, 2026
Kind
B1
Abstract

A first set of timing paths may be selected in an integrated circuit (IC) design. A first set of timing slack values may be calculated for the first set of timing paths across a first set of corners. A dominant corner may be selected in the first set of corners based on the first set of timing slack values. A second set of timing slack values for the dominant corner may be determined for a second set of timing paths in the IC design. A third set of timing slack values may be estimated for the second set of timing paths for non-dominant corners. The third set of timing slack values may be used to select a second set of corners for a timing path in the second set of timing paths, and circuit objects in the timing path may be marked with the second set of corners.

Claims (52)

1 . A method, comprising:

selecting a first set of timing paths in an integrated circuit (IC) design;

calculating a first set of timing slack values and a first set of path component feature values for the first set of timing paths across a first set of corners;

storing the first set of path component feature values for the first set of timing paths in a path library;

selecting a dominant corner in the first set of corners based on the first set of timing slack values;

determining a second set of timing slack values for a second set of timing paths in the IC design for the dominant corner;

estimating a third set of timing slack values for the second set of timing paths across non-dominant corners in the first set of corners based on matching a second set of path component feature values of the second set of timing paths with the first set of path component feature values stored in the path library;

selecting a second set of corners for each timing path in the second set of timing paths based on the third set of timing slack values; and

marking, by a processor, circuit objects in each timing path in the second set of timing paths with the second set of corners corresponding to the timing path.

2 . The method of claim 1 , further comprising propagating timing information to a circuit object in the IC design for corners marked for the circuit object.

3 . The method of claim 1 , further comprising determining an aggressiveness level based on the second set of timing slack values, and wherein the second set of corners are selected based on the third set of timing slack values and the aggressiveness level.

4 . The method of claim 3 , wherein the second set of corners includes more corners when the aggressiveness level is low than when the aggressiveness level is high.

5 . The method of claim 1 , wherein the second set of corners is selected using a cost function.

6 . The method of claim 1 , wherein the second set of timing paths includes a greater number of timing paths than the first set of timing paths.

7 . The method of claim 1 , wherein the estimating the third set of timing slack values comprises:

using a first machine learning model to determine a first result which indicates whether an error in a first timing slack value in the third set of timing slack values is less than a threshold value; and

determining to use a second machine learning model based on the first result, wherein the second machine learning model predicts the first timing slack value in the third set of timing slack values.

8 . A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

select a first set of timing paths in an integrated circuit (IC) design;

calculate a first set of timing slack values and a first set of path component feature values for the first set of timing paths across a first set of corners;

store the first set of path component feature values for the first set of timing paths in a path library;

select a dominant corner in the first set of corners based on the first set of timing slack values;

determine a second set of timing slack values for a second set of timing paths in the IC design for the dominant corner;

estimate a third set of timing slack values for the second set of timing paths across non-dominant corners in the first set of corners based on matching a second set of path component feature values of the second set of timing paths with the first set of path component feature values stored in the path library;

select a second set of corners for each timing path in the second set of timing paths based on the third set of timing slack values; and

mark circuit objects in each timing path in the second set of timing paths with the second set of corners corresponding to the timing path.

9 . The non-transitory computer-readable medium of claim 8 , wherein the instructions further cause the processor to propagate timing information to a circuit object in the IC design for corners marked for the circuit object.

10 . The non-transitory computer-readable medium of claim 8 , wherein the instructions further cause the processor to determine an aggressiveness level based on the second set of timing slack values, and wherein the second set of corners are selected based on the third set of timing slack values and the aggressiveness level.

11 . The non-transitory computer-readable medium of claim 10 , wherein the second set of corners includes more corners when the aggressiveness level is low than when the aggressiveness level is high.

12 . The non-transitory computer-readable medium of claim 8 , wherein the second set of corners is selected using a cost function.

13 . The non-transitory computer-readable medium of claim 8 , wherein the second set of timing paths includes a greater number of timing paths than the first set of timing paths.

14 . The non-transitory computer-readable medium of claim 8 , wherein the estimating the third set of timing slack values comprises:

using a first machine learning model to determine a first result which indicates whether an error in a first timing slack value in the third set of timing slack values is less than a threshold value; and

determining to use a second machine learning model based on the first result, wherein the second machine learning model predicts the first timing slack value in the third set of timing slack values.

15 . An apparatus, comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed causing the processor to:

select a first set of timing paths in an integrated circuit (IC) design;

calculate a first set of timing slack values and a first set of path component feature values for the first set of timing paths across a first set of corners;

store the first set of path component feature values for the first set of timing paths in a path library;

select a dominant corner in the first set of corners based on the first set of timing slack values;

determine a second set of timing slack values for a second set of timing paths in the IC design for the dominant corner, wherein the second 14 set of timing paths includes a greater number of timing paths than the first 15 set of timing paths;

estimate a third set of timing slack values for the second set of timing paths across non-dominant corners in the first set of corners based on matching a second set of path component feature values of the second set of timing paths with the first set of path component feature values stored in the path library;

select a second set of corners for each timing path in the second set of timing paths based on the third set of timing slack values; and

mark circuit objects in each timing path in the second set of timing paths with the second set of corners corresponding to the timing path.

16 . The apparatus of claim 15 , wherein the instructions further cause the processor to propagate timing information to a circuit object in the IC design for corners marked for the circuit object.

17 . The apparatus of claim 15 , wherein the instructions further cause the processor to determine an aggressiveness level based on the second set of timing slack values, and wherein the second set of corners are selected based on the third set of timing slack values and the aggressiveness level.

18 . The apparatus of claim 17 , wherein the second set of corners includes more corners when the aggressiveness level is low than when the aggressiveness level is high.

19 . The apparatus of claim 15 , wherein the second set of corners is selected using a cost function.

20 . The apparatus of claim 15 , wherein the estimating the third set of timing slack values comprises:

using a first machine learning model to determine a first result which indicates whether an error in a first timing slack value in the third set of timing slack values is less than a threshold value; and

determining to use a second machine learning model based on the first result, wherein the second machine learning model predicts the first timing slack value in the third set of timing slack values.