Protecting against emission based side channel detection

1 . A method, in a data processing system, comprising:

parsing, by a logic synthesis engine executing in the data processing system, an integrated (IC) device design data structure specifying an IC device design, to identify at least one instance of an obfuscation indicator in the IC device design data structure, wherein the obfuscation indicator identifies a corresponding IC logic element whose state is to be non-discoverable;

marking, by the logic synthesis engine, at least one IC logic element, in the IC device design, which is associated with the at least one instance of the obfuscation indicator;

selecting, by an emission obfuscation optimization engine executing in the data processing system, at least one emission obfuscation optimization to enable for application to the marked at least one IC logic element, wherein the selection enables one or more emission obfuscation optimizations based on design constraints of the IC device design, a configuration of logic elements and pathways of the IC device design, and emission obfuscation requirements for the at least one IC logic element, the at least one emission obfuscation optimization including replacing at least one target IC logic element having a first voltage threshold that produces a first emissions with at least one replacement IC logic element having a second voltage threshold that produces a second emissions that is lower than the first emissions;

automatically applying, by the emission obfuscation optimization engine executing in the data processing system, the at least one emission obfuscation optimization to the marked at least one IC logic element by relocating the marked at least one IC logic element to a high density region of the IC device design, to modify the IC device design obfuscate emissions from a marked at least one IC device design data structure specifying the modified IC device design;

outputting, by the data processing system, the emissions obfuscated IC device design data structure to a fabrication tool configured to fabricate a physical IC device; and

fabricating, by the fabrication tool, the physical IC device based on the emissions obfuscated IC device design data structure, the physical IC device including at least one physical IC logic element having the at least one emission obfuscation optimization that corresponds to the marked at least one IC logic element.

2 . The method of claim 1 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises relocating the marked at least one IC logic element to a region of the IC device design having relatively larger IC elements providing masking emissions.

3 . The method of claim 1 , wherein automatically applying at the least one emission obfuscation optimization to the marked at least one IC logic element comprises redesigning the marked at least one IC logic element to have a relatively higher threshold voltage.

4 . The method of claim 1 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises redesigning the marked at least one IC logic element to reduce state dependent emission signature changes in an operation of the marked at least one IC logic element.

5 . The method of claim 1 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises at least two different emission obfuscation optimizations selected from a set consisting essentially of:

relocating the marked at least one IC logic element to the high density region of the IC device design;

relocating the marked at least one IC logic element to a region of the IC device design having relatively larger IC elements providing masking emissions; and

redesigning the marked at least one IC logic element to have a relatively higher threshold voltage.

6 . The method of claim 1 , wherein parsing the IC device design data structure to identify the least one instance of an obfuscation indicator in data of the IC device design data structure comprises identifying hardware description language text specifying a secret key pathway in the IC device design, wherein the marked at least one IC logic element is a set of gates along a secure key pathway from an on-chip secure key storage to a locked block of the IC device design, and wherein at least one of the gates is included among the least one target IC logic element having the first voltage threshold that produces the first emissions and is replaced with at least one replacement gate having the second voltage threshold that produces the second emissions that is lower than the first emissions.

7 . The method of claim 1 , wherein the at least one emission obfuscation optimization comprises at least one of adding additional logic elements to the IC device design to obfuscate emissions of the at least one IC logic element while abiding by the design constraints, rearranging existing logic elements in the IC design device to obfuscate emissions of the at least one IC logic element while abiding by the design constraints, redesigning the at least one IC logic element to have a modified operational characteristic that reduces emissions of the at least one IC logic element while abiding by the design constraints, or modifying placement of the existing logic elements and pathways in the IC device design so as to obfuscate emissions of the at least one IC logic element while abiding by the design constraints.

8 . The method of claim 1 , wherein the constraints comprising timing constraints, power consumption constraints, and area constraints for the marked logic elements and other non-marked elements/pathways of the IC design, analyzed in combination with emissions obfuscation requirements of the marked at least one IC logic element.

9 . The method of claim 1 , wherein:

selecting the at least one emission obfuscation optimization comprises selecting a number of emission obfuscation optimizations based on a desired level of security of the marked IC elements,

a first level of security, higher than a second level of security, has a first number of enabled emission obfuscation optimizations and the second level of security has a second number of enabled emission obfuscations, and

the first number is greater than the second number.

10 . A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a data processing system, causes the data processing system to:

parse, by a logic synthesis engine executing in the data processing system, an integrated circuit (IC) device design data structure specifying an IC device design, to identify at least one instance of an obfuscation indicator in the IC device design data structure, and wherein the obfuscation indicator identifies a corresponding IC logic element of those who state is to be non-discoverable;

mark, by the logic synthesis engine, at least one IC logic element, in the IC device design, which is associated with the at least one instance of the obfuscation indicator;

select, by an emission obfuscation optimization engine executing in the data processing system, at least one emission obfuscation optimization to enable for application to the marked at least one IC logic element, wherein the selection enables one or more emission obfuscation optimizations based on design constraints of the IC device design, a configuration of logic elements and pathways of the IC device design, and emission obfuscation requirements for the at least one IC logic element, the at least one emission obfuscation optimization including replacing at least one target IC logic element having a first voltage threshold that produces a first emissions with at least one replacement IC logic element having a second voltage threshold that produces a second emissions that is lower than the first emissions;

automatically apply, by the emission obfuscation optimization engine in the data processing system, the at least one emission obfuscation optimization to the marked at least one IC logic element by relocating the marked at least one IC logic element to a high density region of the IC device design, to modify the IC device design to obfuscate emissions from the marked at least one IC logic element, and generate an emissions obfuscated IC device design data structure specifying the modified IC device;

output, by the data processing system, the emissions obfuscated IC device design data structure to a fabrication tool configured to fabricate a physical IC device in accordance with the emissions obfuscated IC device; and

fabricate, by the fabrication tool, the physical IC device based on the emissions obfuscated IC device design data structure, the physical IC device including at least one physical IC logic element having the at least one emission obfuscation optimization that corresponds to the marked at least one IC logic element.

11 . The computer program product of claim 10 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises relocating the marked at least one IC logic element to a region of the IC device design having relatively larger IC elements providing masking emissions.

12 . The computer program product of claim 10 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises redesigning the marked at least one IC logic element to have a relatively higher threshold voltage.

13 . The computer program product of claim 10 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises redesigning the marked at least one IC logic element to reduce state dependent emission signature changes in an operation of the marked at least one IC logic element.

14 . The computer program product of claim 10 , wherein automatically applying the at least one emission obfuscation optimization to the marked at least one IC logic element comprises at least two different emission obfuscation optimizations selected from a set consisting essentially of:

relocating the marked at least one IC logic element to a high density region of the IC device design;

relocating the marked at least one IC logic element to a region of the IC device design having relatively larger IC elements providing masking emissions; and

redesigning the marked at least one IC logic element to have a relatively higher threshold voltage.

15 . The computer program product of claim 10 , wherein parsing the IC device design data structure to identify the at least one instance of an obfuscation indicator in data of the IC device design data structure comprises identifying hardware description language text specifying a secret key pathway in the IC device design, wherein the marked at least one IC logic element is a set of gates along a secure key pathway from an on-chip secure key storage to a locked logic block of the IC device design, and wherein at least one of the gates is included among the least one target IC logic element having the first voltage threshold that produces the first emissions and is replaced with at least one replacement gate having the second voltage threshold that produces the second emissions that is lower than the first emissions.

16 . The computer program product of claim 10 , wherein the computer readable program further causes the data processing system to:

fabricate the IC device in accordance with the emissions obfuscated IC device design data structure, wherein emissions from IC device elements corresponding to the marked at least one IC logic element are obfuscated against emissions based side channel detection techniques.