Hardware redaction via designer-directed fine-grained embedded field programmable gate array insertion
Disclosed herein is a system and method for using reconfigurable logic for hardware redaction in which the critical IP is obfuscated by replacing it with an eFPGA, thereby entirely concealing the logic and interconnects from reverse engineers and untrusted fabrication facilities. The non-critical intellectual property of the hardware is left unaltered such that the overall VLSI overheads (e.g., area, power, and performance) can be kept to a minimum.
1 . A method for hardware-based redaction of a circuit to obscure redacted portions of the circuit comprising:
receiving an indication of one or more portions of the circuit to be redacted;
determining, for each redacted portion of the circuit, a smallest eFPGA fabric required to map the redacted portion onto an eFPGA;
generating the smallest eFPGA fabric for each of the one or more portions of the circuit to be redacted;
replacing, in a soft design of the circuit, each of the one or more redacted portions of the circuit with the eFPGA fabric generated for that redacted portion to create a mixed ASIC/eFPGA design;
performing a logic synthesis and timing analysis of the mixed ASIC/eFPGA design; and
generating a layout of the redacted circuit, including the eFPGA fabrics generated for each of the redacted portions based on the mixed ASIC/eFPGA design.
2 . The method of claim 1 further comprising:
generating a soft description of the circuit; and
generating a gate-level description of the circuit.
3 . The method of claim 1 wherein the soft design is represented in a hardware description language and wherein the indication of one or more portions of the circuit to be redacted comprises marked portions of the hardware description language describing the one or more redacted portions.
4 . The method of claim 3 wherein the hardware description language is Verilog.
5 . The method of claim 4 wherein the eFPGA fabrics generated for each of the one or more redacted portions do not contain any design details of the redacted portions of the circuit.
6 . The method of claim 5 wherein the hardware description language describing each eFPGA is generated using a fabric generation tool.
7 . The method of claim 6 wherein the fabric generation tool generates static timing analysis constraints for use in synthesizing and optimizing each of the eFPGA fabrics.
8 . The method of claim 7 wherein the fabric generation tool generates the configuration bitstream for each of the eFPGA fabrics.
9 . The method of claim 8 wherein redacted design and static timing analysis constraints are used by a standard ASIC physical design flow to generate the layout of the redacted circuit.
10 . The method of claim 4 wherein the desired functionality of the redacted portions is achieved by loading the eFPGA fabric generated for each of the one or more redacted portions with a configuration bitstream.
11 . The method of claim 3 further comprising:
generating a description of the eFPGA fabric generated for each of the one or more redacted portions in the hardware description language; and
substituting, in the soft design, the hardware description language describing each eFPGA for the hardware description language describing each corresponding redacted portion.
12 . The method of claim 11 wherein generating a description of each eFPGA in the hardware description language comprises:
synthesizing the redacted portions of the hardware design language into lookup tables;
determining a smallest eFPGA fabric size and routing channel width required to map each redacted portion of the circuit onto the eFPGA fabric generated for that redacted portion; and
using the lookup tables to place and route the redacted portions of the circuit with the eFPGA fabric generated for that redacted portion.
13 . The method of claim 11 further comprising:
optimizing the eFPGAs generated for each of the redacted portions based on a target application for one or more of area, performance, power efficiency, reliability and robustness.
14 . The method of claim 13 wherein the eFPGAs generated for the redacted portions are comprised of a plurality of interconnected complex logic blocks and further wherein the optimizing optimizes the complex logic blocks of the eFPGAs, the interconnections of the eFPGAs or both.
15 . The method of claim 13 wherein the optimizing comprises:
generating additional static timing analysis constraints based on a configuration bitstream generated for the eFPGA generated for each of the redacted portions;
using the additional static timing analysis constraints to implement the optimizations of the eFPGA and improve the performance of the redacted portions; and
tuning the additional static timing analysis constraints to optimize the interconnections.
16 . A system comprising:
a processor; and
memory, storing software that when executed by the processor, implements the method of claim 1 .