Parasitic resistance and capacitance extraction methods and non-transitory computer-readable media thereof

1 . A method, comprising:

receiving an electronic layout;

selecting a two-dimensional (2D) conductive element from the electronic layout, wherein a ratio of a width to a length of the selected 2D conductive element is lower than a predetermined threshold, the width is perpendicular to an electrical current direction of the selected 2D conductive element, and the length is parallel to the electrical current direction;

partitioning the selected 2D conductive element into a plurality of polygons, wherein a maximum length of each edge of the plurality of polygons is equal to or smaller than one tenth of a wavelength under a maximum operating frequency;

determining a parasitic capacitance value for each of the plurality of polygons;

determining multiple parasitic resistance values for each of the plurality of polygons;

determining a total capacitance value of the selected 2D conductive element based on the parasitic capacitance value for each of the plurality of polygons;

determining a total resistance value of the selected 2D conductive element based on the multiple parasitic resistance values for each of the plurality of polygons; and

manufacturing a semiconductor device based on the electronic layout.

2 . The method according to claim 1 , wherein the selected 2D conductive element is a metal plate.

3 . The method according to claim 1 , wherein the selected 2D conductive element is a metal plate of a metal insulator metal (MIM) capacitor.

4 . The method according to claim 1 , wherein the selected 2D conductive element includes metal holes.

5 . The method according to claim 1 , wherein the plurality of polygons may comprise triangles or rectangles.

6 . The method according to claim 1 , wherein the wavelength is determined by dividing the speed of light by the maximum operating frequency.

7 . The method according to claim 1 , wherein the maximum operating frequency is 1K Hz or 1M Hz when the selected 2D conductive element is operated under a direct current (DC).

8 . The method according to claim 1 , further comprising:

determining an edge node on each edge of each of the plurality of polygons; and

determining an internal node within an internal area of each polygon.

9 . The method according to claim 8 , wherein the internal node of each of the plurality of polygons is located at a centroid of each polygon.

10 . The method according to claim 8 , wherein, for each of the plurality of polygons, the method further comprises:

determining the parasitic capacitance value of the polygon based on an area of the polygon, wherein the parasitic capacitance value of the polygon is at the internal node.

11 . The method according to claim 8 , wherein, for each of the plurality of polygons, the method further comprises:

partitioning the polygon into a plurality of triangles, each triangle formed by two adjacent vertices of the polygon and the internal node of the polygon, and each triangle including a resistor edge formed by the two adjacent vertices of the polygon; and

for each triangle, based on a length between the resistor edge and the internal node, determining a parasitic resistance value,

wherein the parasitic resistance value of each triangle is between the internal node and the corresponding edge node.

12 . The method according to claim 11 , wherein for each triangle, based on the length between the resistor edge and the internal node, determination of the parasitic resistance value further comprises:

for each triangle, partitioning the triangle into a plurality of rectangles, wherein the plurality of rectangles are arranged parallel to the corresponding resistor edge;

for each triangle, based on widths of the plurality of rectangles parallel to the resistor edge and lengths of the plurality of rectangles perpendicular to the widths, determining resistance values of the plurality of rectangles; and

for each triangle, determining the parasitic resistance value based on resistance values of the plurality of rectangles.

13 . A method, comprising:

receiving an electronic layout;

selecting a three-dimensional (3D) conductive element from the electronic layout;

partitioning the selected 3D conductive element into a plurality of polyhedrons;

determining multiple parasitic capacitance values for each of the plurality of polyhedrons;

determining multiple parasitic resistance values for each of the plurality of polyhedrons;

determining a total capacitance value of the selected 3D conductive element based on the parasitic capacitance values for each of the plurality of polyhedrons;

determining a total resistance value of the selected 3D conductive element based on the multiple parasitic resistance values for each of the plurality of polyhedrons; and

manufacturing a semiconductor device based on the electronic layout.

14 . The method according to claim 13 , wherein, for each of the plurality of polyhedrons, the method further comprises determining one of the parasitic capacitance values based on an area of a face of the polyhedron.

15 . The method according to claim 13 , wherein, for each of the plurality of polyhedrons, the method further comprises:

partitioning the polyhedron into a plurality of tetrahedrons, each of the plurality of tetrahedrons formed by two adjacent edges of the polyhedron and a centroid node of the polyhedron, and each of the plurality of tetrahedrons including a resistor face formed by the two adjacent edges of the polyhedron; and

for each of the plurality of tetrahedrons, based on a length between the resistor face and the centroid node, determining a parasitic resistance value.

16 . The method according to claim 15 , wherein for each of the plurality of tetrahedrons, based on the length between the resistor face and the centroid node, determination of the parasitic resistance value further comprises:

for each of the plurality of tetrahedrons, partitioning the tetrahedron into a plurality of cuboids, wherein the plurality of cuboids are stacked in a first direction orthogonal to the resistor face;

for each of the plurality of tetrahedrons, based on areas of the plurality of cuboids parallel to the resistor face and lengths of the plurality of cuboids in the first direction, determining resistance values of the plurality of cuboids; and

for each of the plurality of tetrahedrons, determining the parasitic resistance value based on resistance values of the plurality of cuboids.

17 . A non-transitory computer-readable medium having stored thereon program instructions that, upon execution by a processor, cause performance of a set of operations comprising:

receiving an electronic layout;

selecting a two-dimensional (2D) conductive element from the electronic layout, wherein a ratio of a width to a length of the selected 2D conductive element is lower than a predetermined threshold, the width is perpendicular to an electrical current direction of the selected 2D conductive element, and the length is parallel to the electrical current direction;

partitioning the selected 2D conductive element into a plurality of polygons, wherein a maximum length of each edge of the plurality of polygons is equal to or smaller than one tenth of a wavelength under a maximum operating frequency;

determining a parasitic capacitance value for each of the plurality of polygons;

determining multiple parasitic resistance values for each of the plurality of polygons;

determining a total capacitance value of the selected 2D conductive element based on the parasitic capacitance value for each of the plurality of polygons;

determining a total resistance value of the selected 2D conductive element based on the multiple parasitic resistance values for each of the plurality of polygons; and

manufacturing a semiconductor device based on the electronic layout.

18 . The non-transitory computer-readable medium according to claim 17 , wherein, for each of the plurality of polygons, the set of operations further comprises determining the parasitic capacitance value of the polygon based on an area of the polygon.

19 . The non-transitory computer-readable medium according to claim 17 , wherein, for each of the plurality of polygons, the set of operations further comprises:

partitioning the polygon into a plurality of triangles, each triangle formed by two adjacent vertices of the polygon and a centroid node of the polygon, and each triangle including a resistor edge formed by the two adjacent vertices of the polygon; and

for each triangle, based on a length between the resistor edge and the centroid node, determining a parasitic resistance value.

20 . The non-transitory computer-readable medium according to claim 19 , wherein for each triangle, based on the length between the resistor edge and the centroid node, determination of the parasitic resistance value further comprises:

for each triangle, partitioning the triangle into a plurality of rectangles, wherein the plurality of rectangles are arranged parallel to the resistor edge;

for each triangle, based on widths of the plurality of rectangles parallel to the resistor edge and lengths of the plurality of rectangles perpendicular to the widths, determining resistance values of the plurality of rectangles; and

for each triangle, determining the parasitic resistance value based on resistance values of the plurality of rectangles.