Semiconductor structure of cell array with adaptive threshold voltage
Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a first regular cell, a second regular cell and a first mixed cell. Each P-type transistor has a first threshold voltage and each N-type transistor has a second threshold voltage in the first regular cell. Each P-type transistor has a third threshold voltage and each N-type transistor has a fourth threshold voltage in the second regular cell. Each P-type transistor has the first threshold voltage and each N-type transistor has the fourth threshold voltage in the first mixed cell. The first regular cell, the second regular cell and the first mixed cell are arranged in the same row of the cell array. The first mixed cell is arranged between the first and second regular cells and is in contact with the first regular cell.
1 . A semiconductor structure, comprising:
a cell array, comprising:
a first mixed cell comprising:
at least one first P-type transistor with a first threshold voltage in an upper region of a first row of the cell array, and at least one first N-type transistor with a second threshold voltage in a lower region of the first row of the cell array; and
at least one second P-type transistor with a third threshold voltage in a lower region of a second row of the cell array, and at least one second N-type transistor with a fourth threshold voltage in a lower region of the second row of the cell array; and
a second mixed cell comprising:
at least one of the second P-type transistor with the third threshold voltage in the upper region of the first row of the cell array, and at least one of the first N-type transistor with the second threshold voltage in the lower region of the first row of the cell array; and
at least one of the second P-type transistor with the third threshold voltage in the lower region of the second row of the cell array, and at least one of the first N-type transistor with the second threshold voltage in the lower region of the second row of the cell array,
wherein the first and second rows of the cell array are the same height,
wherein a first voltage difference between the first and second threshold voltages is different from a second voltage difference between the third and fourth threshold voltages.
2 . The semiconductor structure as claimed in claim 1 , wherein the first and second P-type transistors are surrounded by the first and second N-type transistors in the first mixed cell, and the second P-type transistors are surrounded by the first N-type transistors.
3 . The semiconductor structure as claimed in claim 1 , wherein the second mixed cell has no first P-type transistor or second N-type transistor.
4 . The semiconductor structure as claimed in claim 1 , wherein the cell array further comprises:
a third mixed cell comprising:
at least one of the second P-type transistor with the third threshold voltage and at least one of the second N-type transistor with the fourth threshold voltage in the first row of the cell array; and
at least one of the first P-type transistor with the first threshold voltage and at least one of the first N-type transistor with the second threshold voltage in the second row of the cell array.
5 . The semiconductor structure as claimed in claim 1 , wherein the cell array further comprises:
a fourth mixed cell comprising:
at least one of the first P-type transistor with the first threshold voltage and at least one of the second N-type transistor with the fourth threshold voltage in the first row of the cell array; and
at least one of the first P-type transistor with the first threshold voltage and at least one of the second N-type transistor with the fourth threshold voltage in the second row of the cell array.
6 . The semiconductor structure as claimed in claim 1 , wherein the cell array further comprises:
a first regular cell, wherein each P-type transistor has the first threshold voltage and each N-type transistor has the second threshold voltage in the first and second rows of the cell array.
7 . The semiconductor structure as claimed in claim 1 , wherein the cell array further comprises:
a second regular cell, wherein each P-type transistor has the third threshold voltage and each N-type transistor has the fourth threshold voltage in the first and second rows of the cell array.
8 . The semiconductor structure as claimed in claim 1 , wherein the cell array further comprises:
a third regular cell, wherein each P-type transistor has the first threshold voltage and each N-type transistor has the second threshold voltage in the first row of the cell array; and
a fourth regular cell, wherein each P-type transistor has the third threshold voltage and each N-type transistor has the fourth threshold voltage in the second row of the cell array.
9 . The semiconductor structure as claimed in claim 1 , wherein the third threshold voltage is higher than the first threshold voltage, and the fourth threshold voltage is higher than the second threshold voltage.
10 . The semiconductor structure as claimed in claim 1 , wherein in an arrangement direction of the first row and the second row, the first P-type transistor with the first threshold voltage is between the first N-type transistor with the second threshold voltage and the second P-type transistor with the third threshold voltage.
11 . The semiconductor structure as claimed in claim 1 , wherein in an arrangement direction of the first row and the second row, the second P-type transistor with the third threshold voltage is between the first P-type transistor with the first threshold voltage and the second N-type transistor with the fourth threshold voltage.