IP Library › Granted Patent US 12675679

Granted Patent B2

US 12675679 · App. 17/518,059 · Granted Jul 7, 2026

Crossbar circuit for unaligned memory access in neural network processor

Inventors: Paolo Di Febbo (Redwood City, CA); Anthony Ghannoum (Santa Clara, CA)

Assignee: APPLE INC.

G06N3/063 G06F5/06 G11C7/1012 G11C11/40 G11C11/54

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Quick Facts

Patent No.: US 12675679
App. No.: 17/518,059
Granted: Jul 7, 2026
Kind: B2

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Abstract

Embodiments of the present disclosure relate to an unaligned memory access in a neural processor circuit. The neural processor circuit includes a crossbar circuit and a neural engine circuit coupled to the crossbar circuit. During each operating cycle of the neural processor circuit, the crossbar circuit receives a portion of input data, and re-aligns or bypasses the portion of input data. The neural engine circuit receives at least a portion of the re-aligned or bypassed portion of the input data, and performs a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

Claims (70)

1 . A neural processor circuit, comprising:

a data processor circuit, the data processor circuit comprising:

a buffer memory configured to store input data comprising a plurality of data elements, wherein a data element occupies a location of the buffer memory that is addressed by a data address; and

an address decoder circuit coupled to the buffer memory and configured to decode one or more address components of an address for the buffer memory including a most significant address component to generate a decoded address for the buffer memory to access a portion of input data comprising multiple data elements of the plurality of data elements;

a crossbar circuit coupled to the data processor circuit and configured, during each operating cycle, to receive one or more address components of the address including a least significant address component, and further receive the portion of input data from the buffer memory based on the decoded address, and re-align the multiple data elements of the portion of input data accessed by the decoded address or bypass the portion of input data, wherein the crossbar circuit is directly coupled to the data processor circuit and a neural engine circuit, bypassing cache or buffer components, to reduce power consumption by the neural engine circuit; and

the neural engine circuit coupled to the crossbar circuit, the neural engine circuit configured to receive at least a portion of the re-aligned or bypassed portion of the input data, and perform a convolution operation on the received portion of the re-aligned or bypassed portion of input data to generate output data.

2 . The neural processor circuit of claim 1 , wherein the crossbar circuit is further configured to:

re-align the portion of input data by reordering at least a portion of a plurality of sets of the portion of input data by a defined number of bytes.

3 . The neural processor circuit of claim 2 , wherein each set of the portion of input data comprises a same number of bytes of the portion of input data.

4 . The neural processor circuit of claim 1 , wherein:

the one or more address components including the most significant address component provided to the address decoder circuit to generate the decoded address and the one or more address components including the least significant address component provided to the crossbar circuit share at least a common address component; and

the address decoder circuit is configured, during each operating cycle, to

initiate loading of the portion of input data from the buffer memory to the crossbar circuit in accordance with the decoded address.

5 . The neural processor circuit of claim 4 , wherein the data processor circuit further comprises an address splitter circuit coupled to the address decoder circuit and the crossbar circuit, the address splitter circuit being configured, during each operating cycle, to:

split the address into a plurality of address components; and

configure the crossbar circuit to re-align or bypass the portion of input data based on the one or more address components including the least significant address component from the address splitter circuit.

6 . The neural processor circuit of claim 1 , wherein the crossbar circuit comprises a pair of crossbar units connected in series, each crossbar unit comprising a plurality of switches configured to re-align or bypass the portion of input data.

7 . The neural processor circuit of claim 1 , wherein the crossbar circuit is further configured to:

receive the output data from the neural engine circuit; and

write the received output data into the data processor circuit.

8 . The neural processor circuit of claim 7 , wherein the crossbar circuit is further configured to:

re-align the received output data prior to writing the received output data into the data processor circuit.

9 . The neural processor circuit of claim 1 , further comprising a data bus coupled to outputs of the crossbar circuit and inputs of the neural engine circuit, wherein:

the crossbar circuit is further configured to provide, during each operating cycle, the re-aligned or bypassed portion of input data onto the data bus; and

the neural engine circuit is further configured to receive the portion of the re-aligned or bypassed portion of input data from the data bus.

10 . The neural processor circuit of claim 1 , further comprising a data bus coupled to outputs of the crossbar circuit, wherein the crossbar circuit is further configured, during each operating cycle, to:

receive the portion of input data from the data processor circuit; and

re-align or bypass the received portion of input data such that any re-aligned or bypassed version of the portion of input data is output onto the data bus.

11 . A method of operating a neural processor circuit, comprising:

storing, in a buffer memory of a data processor circuit, input data comprising a plurality of data elements, wherein a data element occupies a location of the buffer memory that is addressed by a data address;

decoding, by an address decoder circuit of the data processor circuit, one or more address components of an address for the buffer memory including a most significant address component to generate a decoded address for the buffer memory to access a portion of input data comprising multiple data elements of the plurality of data elements;

receiving, by a crossbar circuit, one or more address components including a least significant address component generated from the address for the buffer memory;

receiving, by the crossbar circuit, the portion of input data from the buffer memory based on the decoded address during each operating cycle;

re-aligning the multiple data elements of the portion of input data accessed by the decoded address or bypassing the portion of input data by the crossbar circuit during each operating cycle;

receiving, at a neural engine circuit coupled to the crossbar circuit, at least a portion of the re-aligned or bypassed portion of input data, wherein the crossbar circuit is directly coupled to the data processor circuit and the neural engine circuit, bypassing cache or buffer components, to reduce power consumption by the neural engine circuit; and

performing, by the neural engine circuit, a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

12 . The method of claim 11 , further comprising:

re-aligning, by the crossbar circuit, the portion of input data by reordering at least a portion of a plurality of sets of the portion of input data by a defined number of bytes.

13 . The method of claim 11 , further comprising:

loading, during each operating cycle, the portion of input data from the buffer memory to the crossbar circuit in accordance with the decoded address, wherein the one or more address components including the most significant address component provided to the address decoder circuit to generate the decoded address and the one or more address components including the least significant address component provided to the crossbar circuit share at least a common address component.

14 . The method of claim 13 , further comprising:

splitting, during each operating cycle by an address splitter circuit coupled to the address decoder circuit and the crossbar circuit, the address into a plurality of address components;

configuring, during each operating cycle, the crossbar circuit to re-align or bypass the portion of input data based on the one or more address components including the least significant address component from the address splitter circuit.

15 . The method of claim 11 , further comprising:

receiving the output data from the neural engine circuit at the crossbar circuit; and

writing, via the crossbar circuit, the received output data into the data processor circuit coupled to the crossbar circuit.

16 . The method of claim 15 , further comprising:

re-aligning, by the crossbar circuit, the received output data prior to writing the received output data into the data processor circuit.

17 . The method of claim 11 , further comprising:

providing, by the crossbar circuit during each operating cycle, the re-aligned or bypassed portion of input data onto a data bus coupled to outputs of the crossbar circuit and inputs of the neural engine circuit; and

receiving, at the neural engine circuit, the portion of the re-aligned or bypassed portion of input data from the data bus.

18 . The method of claim 11 , further comprising:

re-aligning or bypassing, during each operating cycle, the received portion of input data such that any re-aligned or bypassed version of the portion of input data is output onto a data bus coupled to outputs of the crossbar circuit.

19 . An electronic device, comprising:

a system memory storing input data; and

a neural processor circuit coupled to the system memory, the neural processor circuit including:

a data processor circuit, the data processor circuit comprising:

a buffer memory configured to store input data comprising a plurality of data elements, wherein a data element occupies a location of the buffer memory that is addressed by a data address; and

a neural engine circuit coupled to the crossbar circuit, wherein the crossbar circuit is directly coupled to the data processor circuit and the neural engine circuit, bypassing cache or buffer components, to reduce power consumption by the neural engine circuit, the neural engine circuit configured to:

receive at least a portion of the re-aligned or bypassed portion of input data, and

perform a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

20 . The electronic device of claim 19 , wherein the data processor circuit includes an address splitter circuit coupled to the address decoder circuit and the crossbar circuit, wherein:

the address decoder circuit is configured, during each operating cycle, to:

initiate loading of the portion of input data from the buffer memory to the crossbar circuit in accordance with the decoded address;

the address splitter circuit is configured, during each operating cycle, to:

split the address into a plurality of address components, and

the crossbar circuit is further configured to re-align the portion of input data by reordering at least a portion of a plurality of sets of the portion of input data by a defined number of bytes.