Function approximation unit configured to approximate nonlinear functions in a neural processing unit and operating method thereof
Methods and devices of a function approximation unit configured to approximate a nonlinear function within a neural processing unit are described. According to one embodiment, the method includes storing an input value through an input register of the function approximation unit, transmitting the input value to a selected one of a plurality of preprocessing circuits of the unit according to a control signal, generating a preprocessing result corresponding to the input value by the selected one of the preprocessing circuits, transmitting the preprocessing result to a programmable function approximation circuit and a selected one of a plurality of post-processing circuits of the unit, generating an approximated function output based on the preprocessing result in the programmable function approximation circuit, and generating a final output value by post-processing the preprocessing result or the approximated function output in the selected one of the post-processing circuits.
1 . An operating method of a function approximation unit configured to approximate a nonlinear function within a neural processing unit,
wherein the function approximation unit comprises
an input register,
a plurality of preprocessing circuits respectively dedicated to different nonlinear functions and configured to perform a function-specific preprocessing including a reciprocal function, a reciprocal of a square root function, or a negative exponential function,
a single shared programmable function approximation circuit configured to approximate only a mantissa component using a comparator-based segmentation scheme, and
a plurality of post-processing circuits respectively paired with the plurality of preprocessing circuits and configured to perform a function-specific post-processing, and
the method comprises:
storing an input value through the input register;
transmitting the input value to a selected one of the plurality of preprocessing circuits according to a control signal;
generating a preprocessing result corresponding to the input value by the selected one of the plurality of preprocessing circuits;
transmitting the preprocessing result to the single shared programmable function approximation circuit and a selected one of the plurality of post-processing circuits;
generating an approximated function output based on the preprocessing result in the single shared programmable function approximation circuit; and
generating a final output value by post-processing the preprocessing result or the approximated function output in the selected one of the plurality of post-processing circuits.
2 . The operating method of claim 1 , wherein the control signal has a length of two bits and is used to select the selected one of the plurality of preprocessing circuits.
3 . The operating method of claim 1 , wherein the single shared programmable function approximation circuit is configured to receive an output received from the plurality of preprocessing circuits through a multiplexer and perform an approximation operation according to the preprocessing result.
4 . The operating method of claim 1 , wherein the single shared programmable function approximation circuit selectively receives one of a plurality of programmable parameter sets and performs an approximation operation on the preprocessing result.
5 . The operating method of claim 1 , wherein the function approximation unit further comprises an intermediate register that stores the preprocessing result and an output of the single shared programmable function approximation circuit, and
the method comprises transmitting an output of the intermediate register and an output of the plurality of preprocessing circuits to one of the plurality of post-processing circuits according to a control signal thereof.
6 . The operating method of claim 1 , wherein each of the plurality of preprocessing circuits comprise a first decomposition circuit, a first decoder, and an input value generation circuit.
7 . The operating method of claim 1 , wherein each of the plurality of post-processing circuits comprise an exponent conversion circuit, a second decomposition circuit, a second decoder, an adder, an encoder, and a concatenation circuit.
8 . The operating method of claim 1 , wherein the function approximation unit further comprises a demultiplexer for selecting one of the plurality of post-processing circuits according to a control signal thereof.
9 . The operating method of claim 1 , further comprising transmitting the final output value to an output register of the function approximation unit through a multiplexer and storing the final output value.
10 . The operating method of claim 1 , wherein the plurality of preprocessing circuits and the plurality of post-processing circuits are variably configured according to a function type.
11 . A function approximation device configured to approximate a nonlinear function within a neural processing unit, comprising:
an input register to receive and store an input value;
a plurality of preprocessing circuits respectively dedicated to different nonlinear functions and configured to perform a function-specific preprocessing including a reciprocal function, a reciprocal of a square root function, or a negative exponential function,
wherein the input value from the input register is transmitted to a selected one of the plurality of preprocessing circuits;
a single shared programmable function approximation circuit configured to approximate only a mantissa component using a comparator-based segmentation scheme and to generate an approximated function output based on a preprocessing result generated by the selected one of the plurality of preprocessing circuits;
a plurality of post-processing circuits respectively paired with the plurality of preprocessing circuits and configured to perform a function-specific post-processing for the reciprocal function, the reciprocal of the square root function, or the negative exponential function,
wherein the preprocessing result by the selected one of the plurality of preprocessing circuits and the approximated function output from the single shared programmable function approximation circuit are transmitted to a selected one of the plurality of post-processing circuits; and
an output register to receive and store an output from the selected one of the plurality of post-processing circuits.
12 . The function approximation device of claim 11 , further comprising a first demultiplexer to transmit the input value from the input register to the selected one of the plurality of preprocessing circuits according to a control signal thereof.
13 . The function approximation device of claim 12 , wherein the first demultiplexer transmits the input value to the selected one of the plurality of preprocessing circuits based on a two-bit control signal.
14 . The function approximation device of claim 11 , further a comprising a first multiplexer and a second multiplexer,
wherein the first multiplexer is configured to receive the preprocessing result output by the selected one of the plurality of preprocessing circuits and selectively transmit the preprocessing result to the single shared programmable function approximation circuit or the plurality of post-processing circuits.
15 . The function approximation device of claim 14 , further comprising an intermediate register to store a function approximation operation result output by the single shared programmable function approximation circuit.
16 . The function approximation device of claim 15 , further comprising a second demultiplexer to transmit an output from the intermediate register and a second multiplexer to the selected one of the plurality of post-processing circuits according to a control signal thereof.
17 . The function approximation device of claim 11 , wherein each of the plurality of preprocessing circuits comprises a first decomposition circuit, a first decoder, and an input value generation circuit.
18 . The function approximation device of claim 11 , wherein each of the plurality of post-processing circuits comprises an exponent conversion circuit, a second decomposition circuit, a decoder, an adder, an encoder, and a concatenation circuit.
19 . The function approximation device of claim 11 , wherein the plurality of preprocessing circuits and the plurality of post-processing circuits are variably configured according to an external setting or an internal operation condition.