Ahead-of-time gate-fusion transpilation for simulation

1 . A computer-implemented method of gate-fusion transpilation, the method comprising:

receiving, by a system comprising a processor, a quantum circuit data representing a quantum circuit;

compiling, by the system, the quantum circuit data into a format compatible with a simulated operation of the quantum circuit;

generating, by the system, a cache key for the quantum circuit from the compiled quantum circuit data, wherein generating the cache key comprises:

determining the cache key based on a number of gate operations, types of gates, and target qubits of the gate operations in the quantum circuit without using parameter values of any quantum gate operations in the quantum circuit;

checking for an equivalence of the quantum circuit by comparing the cache key to stored cache keys in a cache;

based on the checking:

retrieving and executing, by the system, a gate-fusion transpilation procedure based on a configuration of the quantum circuit, in response to determining that the gate-fusion transpilation procedure associated with a stored cache key matching the cache key is pre-stored in the cache, or

creating and executing, by the system, the gate-fusion transpilation procedure based on the configuration of the quantum circuit, in response to determining that none of the stored cache keys in the cache matches the cache key;

performing, by the system, the simulated operation of the quantum circuit; and

outputting, by the system, a result of the simulated operation of the quantum circuit.

2 . The computer-implemented method according to claim 1 , wherein the gate-fusion transpilation procedure performs a fusing of data of a first quantum gate with one or more additional quantum gates into a fused gate based on a gate fusion strategy.

3 . The computer-implemented method according to claim 2 , further comprising storing the created gate fusion transpilation procedure in the cache.

4 . The computer-implemented method according to claim 1 , wherein generating the cache key is performed by using a sequence number, a gate type, and a target qubit of each gate operation of the quantum circuit.

5 . The computer-implemented method according to claim 1 , wherein the gate-fusion transpilation procedure includes generating a cache value table from a source gate and a target gate of fused gates.

6 . The computer-implemented method according to claim 5 , wherein the cache value table includes a sequential number, a fusion method, and a listing of the fused gates for each sequence number.

7 . The computer-implemented method according to claim 1 , wherein the quantum circuit is identified as an original quantum circuit, and the method further comprising generating, by the transpilation procedure, an enhanced quantum circuit comprising fewer gate operations than the original quantum circuit.

8 . The computer-implemented method according to claim 7 , wherein the generated enhanced quantum circuit includes a same quantity of gate operations as a quantity of fused gates.

9 . A system comprising:

a processor;

a memory coupled to the processor, the memory storing instructions to cause the processor to perform operations comprising:

receiving a quantum circuit data representing a quantum circuit,

compiling the quantum circuit data into a format compatible with a simulated operation of the quantum circuit;

generating a cache key for the quantum circuit from the compiled quantum circuit data, wherein generating the cache key comprises:

determining the cache key based on a number of gate operations, types of gates, and target qubits of the gate operations in the quantum circuit without using parameter values of any quantum gate operations in the quantum circuit;

checking for an equivalence of the quantum circuit by comparing the cache key to stored cache keys in a cache;

based on the checking:

retrieving and executing a gate-fusion transpilation procedure based on a configuration of the quantum circuit in response to determining that the gate-fusion transpilation procedure associated with a stored cache key matching the cache key is pre-stored in the cache, or

creating and executing the gate-fusion transpilation procedure based on the configuration of the quantum circuit in response to determining that none of the stored cache keys in the cache matches the cache key;

performing the simulated operation of the quantum circuit; and

outputting a result of the simulated operation of the quantum circuit.

10 . The computing device according to claim 9 , wherein the operations further comprise:

fusing of the quantum circuit data of a first quantum gate with the quantum circuit data of one or more additional quantum gates into a unitary-gate based on a gate fusion strategy.

11 . The computing device according to claim 9 , wherein the operations further comprise:

storing the created gate fusion transpilation procedure in the cache.

12 . The computing device according to claim 11 , wherein the operations further comprise:

generating the cache key by using a sequence number, a gate type, and a target qubit of each gate operation of the quantum circuit.

13 . The computing device according to claim 9 , wherein the operations further comprise: generating a cache value table from a source gate and a target gate of fused gates.

14 . The computing device according to claim 9 , wherein operations further comprise: including in the cache value table a sequential number, a fusion method and a listing of the fused gates for each sequence number.

15 . The computing device according to claim 9 , wherein the operations further comprise:

identifying the quantum circuit as an original quantum circuit; and

generating an enhanced quantum circuit comprising fewer gate operations than the original quantum circuit.

16 . A non-transitory computer readable medium having instructions stored thereon that, in response to execution, causes a system comprising a processor to perform operations comprising:

receiving a quantum circuit data representing a quantum circuit,

compiling the quantum circuit data into a format compatible with a simulated operation of the quantum circuit;

generating a cache key for the quantum circuit from the compiled quantum circuit data, wherein generating the cache key comprises:

determining the cache key based on a number of gate operations, types of gates, and target qubits of the gate operations in the quantum circuit without using parameter values of any quantum gate operations in the quantum circuit;

checking for an equivalence of the quantum circuit by comparing the cache key to stored cache keys in a cache;

based on the checking:

retrieving and executing a gate-fusion transpilation procedure based on a configuration of the quantum circuit in response to determining that the gate-fusion transpilation procedure associated with a stored cache key matching the cache key is pre-stored in the cache, or

creating and executing the gate-fusion transpilation procedure based on the configuration of the quantum circuit in response to determining that none of the stored cache keys in the cache matches the cache key;

performing the simulated operation of the quantum circuit; and

outputting a result of the simulated operation of the quantum circuit.

17 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise:

fusing of the quantum circuit data of a first quantum gate with the quantum circuit data of one or more additional quantum gates into a unitary-gate based on a gate fusion strategy.

18 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise:

storing the created gate fusion transpilation procedure in the cache.

19 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise:

generating the cache key by using a sequence number, a gate type, and a target qubit of each gate operation of the quantum circuit.

20 . The non-transitory computer readable medium of claim 19 , wherein the operations further comprise:

generating a cache value table from a source gate and a target gate of fused gates.