Demodulation circuit and server

1 . A demodulation circuit, comprising an analysis circuit, a sampling circuit, and a sampling control circuit, wherein the sampling circuit is respectively connected to the analysis circuit and the sampling control circuit;

the analysis circuit is configured to receive a first signal outputted by a hard disk state pin, and analyze a high-level signal and a low-level signal in the first signal, so as to obtain a first pulse width corresponding to the high-level signal and a second pulse width corresponding to the low-level signal, wherein the first signal includes hard disk data; and

the sampling control circuit is configured to trigger, according to the first signal, the sampling circuit to sample the first pulse width and the second pulse width such that the hard disk data corresponding to the first signal is analyzed according to the sampled first pulse width and second pulse width, so as to realize the monitoring of a hard disk.

2 . The demodulation circuit according to claim 1 , wherein the analysis circuit comprises a charging loop and a discharging loop; the demodulation circuit further comprises a loop control circuit, and the charging loop is respectively connected to the sampling control circuit, the loop control circuit, and the discharging loop;

the charging loop is configured to perform charging according to a preset level signal in the first signal to obtain an i-th pulse width, in a case that the charging loop is turned on;

the discharging loop is configured to perform discharging according to a non-preset level signal in the first signal, in a case that the discharging loop is turned on;

the sampling control circuit is configured to trigger the sampling circuit to sample the i-th pulse width by delaying a first time after the charging loop completes charging;

the loop control circuit is configured to control the discharging loop to turn on by delaying a second time after the sampling control circuit triggers the sampling circuit to sample the i-th pulse width; and

in a case that the preset level signal is the high-level signal, i is one, and in a case that the preset level signal is the low-level signal, i is two.

3 . The demodulation circuit according to claim 2 , wherein in a case that the preset level signal is the high-level signal and the loop control circuit detects a rising edge of the first signal, the loop control circuit controls the charging loop to turn on; in a case that the preset level signal is the high-level signal and the loop control circuit detects a falling edge of the first signal, the loop control circuit triggers the sampling circuit to sample the first pulse width; and in a case that the preset level signal is the low-level signal, the loop control circuit receives the first signal via a first phase inverter, controls the charging loop to turn on when detecting a rising edge outputted by the first phase inverter, and triggers the sampling circuit to sample the second pulse width when detecting a falling edge outputted by the first phase inverter.

4 . The demodulation circuit according to claim 2 , wherein the first signal is a signal that is obtained through modulation by the hard disk according to hard disk log data and a hard disk state signal corresponding to the hard disk state pin; the hard disk state pin continuously outputs a first control signal at a first level in a case that the hard disk is in a preset state, and outputs a second control signal in a case that the hard disk is in a non-preset state, wherein the second control signal is a rectangular wave signal; in a case that the hard disk is in the preset state, the hard disk inserts a plurality of pulse signals at a second level in the first control signal, and then segments the first control signal by using the pulse signals, so as to obtain the first signal; in a case that the hard disk is in the non-preset state, codes each data bit in the hard disk log data into a level signal with a preset width corresponding to each data bit, so as to obtain the first signal;

the demodulation circuit further comprises a detection circuit, wherein the detection circuit is respectively connected to the sampling control circuit and the loop control circuit; and

the detection circuit is configured to detect whether the pulse signal is present in the first signal, and adjust the first time and/or the second time according to a detection result.

5 . The demodulation circuit according to claim 4 , wherein the manner of coding each data bit into the level signal with the preset width comprises:

coding each data bit into a pulse width signal with a corresponding duty cycle; or

coding each data bit into the level signal with the preset width, and inserting an opposite level signal with a certain width between two adjacent data bits in a case that the level signals of the two adjacent data bits are opposite or the level signals of the two adjacent data bits are the same.

6 . The demodulation circuit according to claim 4 , wherein the detection circuit is configured to control the sampling control circuit to operate in a first mode in a case that determining that the pulse signal is present in the first signal, and control the sampling control circuit to operate in a second mode in a case that determining that the pulse signal is not present in the first signal; and

after the charging loop completes charging, the sampling control circuit is configured to, trigger the sampling circuit to sample the i-th pulse width by delaying a first preset time, in a case that the sampling control circuit is in the first mode; and trigger the sampling circuit to sample the i-th pulse width by delaying a second preset time, in a case that the sampling control circuit is in the second mode, wherein the first preset time is less than the second preset time, and the first time is the first preset time or the second preset time.

7 . The demodulation circuit according to claim 4 , wherein the detection circuit is configured to control the loop control circuit to operate in a third mode in a case that determining that the pulse signal is present in the first signal, and control the loop control circuit to operate in a fourth mode in a case that determining that the pulse signal is not present in the first signal; and

after the sampling control circuit triggers the sampling circuit to sample the i-th pulse width, the loop control circuit is configured to control the discharging loop to turn on by delaying a third preset time, in a case that the loop control circuit is in the third mode; and control the discharging loop to turn on by delaying a fourth preset time, in a case that the loop control circuit is in the fourth mode, wherein the third preset time is less than the fourth preset time, and the second time is the third preset time or the fourth preset time.

8 . The demodulation circuit according to claim 4 , wherein the detection circuit comprises a first integration circuit, a comparison circuit, and a trigger circuit; the trigger circuit is respectively connected to the sampling control circuit and the loop control circuit;

the first integration circuit is configured to integrate a signal at the second level in the first signal, so as to obtain a first integral value;

the comparison circuit is configured to compare the first integral value with a first preset integral value and a second preset integral value, output a first triggering signal in a case that the first integral value being greater than the first preset integral value, and output a second triggering signal in a case that the first integral value being greater than the second preset integral value, wherein the first preset integral value is less than the second preset integral value; and

the trigger circuit is configured to adjust the first time and/or the second time according to the first triggering signal or the second triggering signal.

9 . The demodulation circuit according to claim 4 , wherein the loop control circuit comprises a time-delay circuit and a logic circuit;

an output end of the time-delay circuit is connected to a first input end of the logic circuit, a control end of the time-delay circuit is connected to the detection circuit, a second input end of the logic circuit is connected to the hard disk state pin, and an output end of the logic circuit is respectively connected to the charging loop and the discharging loop;

the time-delay circuit is configured to output the first signal by delaying the second time;

the logic circuit is configured to perform a logical operation according to a first signal outputted by the time-delay circuit and a first signal outputted by the hard disk state pin, so as to output a first turn-on signal when detecting a starting edge of a preset level signal of the first signal outputted by the hard disk state pin, and output a second turn-on signal when detecting an end edge of a preset level signal of the first signal outputted by the time-delay circuit;

the charging loop is configured to be turned on in a case that receiving the first turn-on signal to perform charging according to the preset level signal, so as to obtain the i-th pulse width; and

the discharging loop is configured to be turned on in a case that receiving the second turn-on signal to perform discharging according to the non-preset level signal.

10 . The demodulation circuit according to claim 9 , wherein the charging loop comprises a first charging loop and a second charging loop, and the discharging loop comprises a first discharging loop and a second discharging loop;

a first output end of the logic circuit is respectively connected to a control end of the first charging loop and a control end of the first discharging loop; the hard disk state pin is respectively connected to an input end of the first charging loop, an input end of the first discharging loop, an input end of the second charging loop, and an input end of the second discharging loop; the sampling circuit is respectively connected to an output end of the first charging loop and an output end of the second charging loop; and a second output end of the logic circuit is connected to a control end of the second charging loop and a control end of the second discharging loop, respectively;

the first charging loop is configured to be turned on in a case that the logic circuit detects a rising edge of the first signal outputted by the hard disk state pin, so as to start charging, and be cut off in a case that the logic circuit detects a falling edge of the first signal outputted by the hard disk state pin, so as to stop charging, thereby obtaining a first charging voltage value corresponding to the high-level signal;

the first discharging loop is configured to be turned on in a case that the logic circuit detects a falling edge of the first signal outputted by the time-delay circuit, so as to start discharging;

the second charging loop is configured to be turned on in a case that the logic circuit detects the falling edge of the first signal outputted by the hard disk state pin, so as to start charging, and be cut off in a case that the logic circuit detects the rising edge of the first signal outputted by the hard disk state pin, so as to stop charging, so as to obtain a second charging voltage value corresponding to the low-level signal in the first signal;

the second discharging loop is configured to be turned on in a case that the logic circuit detects a rising edge of the first signal outputted by the time-delay circuit, so as to start discharging; and

the sampling control circuit is configured to trigger the sampling circuit to sample the first charging voltage value by delaying the first time after the first charging loop completes charging, and trigger the sampling circuit to sample the second charging voltage value after the second charging loop completes charging.

11 . The demodulation circuit according to claim 10 , wherein in a case that a second integration circuit comprises the first charging loop and the first discharging loop, a circuit structure of the second integration circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a first switch, and a first amplifier;

a first end of the first resistor is connected to the hard disk state pin, and a second end of the first resistor is respectively connected to an input negative end of the first amplifier, a first end of the first capacitor, and a first end of the third resistor; a second end of the third resistor is connected to a first end of the first switch, and a second end of the first switch is respectively connected to a second end of the first capacitor and an output end of the first amplifier; a first end of the second resistor is grounded, and a second end of the second resistor is connected to an input positive end of the first amplifier; a control end of the first switch is connected to the output end of the logic circuit; and

the first switch is configured to be disconnected in a case that the logic circuit detects the rising edge of the first signal outputted by the hard disk state pin such that the first capacitor is charged via the first resistor, and be turned off in a case that the logic circuit detects the falling edge of the first signal outputted by the time-delay circuit such that the first capacitor is discharged via the third resistor.

12 . The demodulation circuit according to claim 10 , wherein in a case that a third integration circuit comprises the second charging loop and the second discharging loop, a circuit structure of the third integration circuit comprises a first phase inverter, a fourth resistor, a fifth resistor, a sixth resistor, a second capacitor, a second switch, and a second amplifier;

a first end of the fourth resistor is connected to the hard disk state pin via the first phase inverter, and a second end of the fourth resistor is respectively connected to an input negative end of the second amplifier, a first end of the second capacitor, and a first end of the sixth resistor; a second end of the sixth resistor is connected to a first end of the second switch, and a second end of the second switch is respectively connected to a second end of the second capacitor and an output end of the second amplifier; a first end of the fifth resistor is grounded, and a second end of the fifth resistor is connected to an input positive end of the second amplifier; a control end of the second switch is connected to the output end of the logic circuit; and

the second switch is configured to be disconnected in a case that the logic circuit detects the falling edge of the first signal outputted by the hard disk state pin such that the second capacitor is charged via the fourth resistor, and be turned off in a case that the logic circuit detects the rising edge of the first signal outputted by the time-delay circuit such that the second capacitor is discharged via the sixth resistor.

13 . The demodulation circuit according to claim 6 , wherein the sampling control circuit comprises a seventh resistor, an eighth resistor, a ninth resistor, a third capacitor, a sixth capacitor, a third switch, and a first comparator;

a first end of the ninth resistor is connected to the hard disk state pin, and a second end of the ninth resistor is respectively connected to a first end of the third switch and an input positive end of the first comparator; a second end of the third switch is grounded via the third capacitor, and a third end of the third switch is grounded via the sixth capacitor; a first end of the seventh resistor is connected to a power supply module, and a second end of the seventh resistor is connected to a first end of the eighth resistor and an input negative end of the first comparator, respectively; a second end of the eighth resistor is grounded; an output end of the first comparator is connected to the sampling circuit; a capacitance value of the third capacitor is greater than a capacitance value of the sixth capacitor; and

the first end and second end of the third switch are turned on in a case that the sampling control circuit operates in the second mode, and the first end and third end of the third switch are turned on in a case that the sampling control circuit operates in the first mode.

14 . The demodulation circuit according to claim 9 , wherein the time-delay circuit comprises a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, a seventh capacitor, a fourth switch, and a second comparator;

a first end of the tenth resistor is connected to a power supply module, and a second end of the tenth resistor is respectively connected to a first end of the eleventh resistor and an input negative end of the second comparator; a second end of the eleventh resistor is grounded; a first end of the twelfth resistor is connected to an output end of the sampling control circuit, and a second end of the twelfth resistor is respectively connected to a first end of the fourth switch and an input positive end of the second comparator; a second end of the fourth switch is grounded via the fourth capacitor, and a third end of the fourth switch is grounded via the seventh capacitor; an output end of the second comparator is connected to the first input end of the logic circuit; a capacitance value of the fourth capacitor is greater than a capacitance value of the seventh capacitor; and

the first end and second end of the fourth switch are turned on in a case that the time-delay circuit operates in the fourth mode, and the first end and third end of the fourth switch are turned on in a case that the fourth operates in the third mode.

15 . The demodulation circuit according to claim 9 , wherein the logic circuit comprises a second phase inverter, a third phase inverter, a first AND gate, and a second AND gate;

an input end of the second phase inverter is connected to the hard disk state pin, and an output end of the second phase inverter is connected to a first input end of the first AND gate; an input end of the third phase inverter is connected to the output end of the time-delay circuit, and an output end of the third phase inverter is connected to a second input end of the first AND gate; an output end of the first AND gate is the first output end of the logic circuit; and a first input end of the second AND gate is connected to the hard disk state pin, a second input end of the second AND gate is connected to the output end of the time-delay circuit, and an output end of the second AND gate is the second output end of the logic circuit.

16 . The demodulation circuit according to claim 8 , wherein the first integration circuit comprises a third amplifier, a fifth capacitor, and a thirteenth resistor; the comparison circuit comprises a third comparator, a fourth comparator, a first reference circuit, and a second reference circuit; the trigger circuit comprises a trigger;

a first end of the thirteenth resistor is connected to the hard disk state pin via a first phase inverter, a second end of the thirteenth resistor is respectively connected to an input positive end of a third amplifier and a first end of the fifth capacitor; a second end of the fifth capacitor is grounded; an input negative end of the third amplifier is respectively connected to an output end of the third amplifier, an input negative end of the third comparator, and an input negative end of the fourth comparator; an input positive end of the third comparator is connected to the first reference circuit; an input positive end of the fourth comparator is connected to the second reference circuit; an output end of the third comparator is connected to a first input end of the trigger; an output end of the fourth comparator is connected to a second input end of the trigger; an output end of the trigger is an output end of the detection circuit; a first reference voltage outputted by the first reference circuit is less than a second reference voltage outputted by the second reference circuit.

17 . The demodulation circuit according to claim 1 , wherein the first signal is a signal that is obtained through modulation by the hard disk according to the hard disk log data and the hard disk state signal corresponding to the hard disk state pin; the hard disk state pin is a state indicator lamp pin of the hard disk; the state indicator lamp pin continuously outputs the first control signal at the first level in a case that the hard disk is in the preset state, and outputs the second control signal in a case that the hard disk is in the non-preset state such that a state indicator lamp flashes; the second control signal is the rectangular wave signal;

the hard disk in the preset state, inserts the plurality of pulse signals at the second level in the first control signal at the first level, and segments the first control signal by using the pulse signals, so as to obtain the first signal; the hard disk in the non-preset state, codes each data bit in the hard disk log data into the level signal with the preset width corresponding to each data bit, so as to obtain the first signal; and

the demodulation circuit further comprises:

an indicator lamp drive circuit, connected to the state indicator lamp, wherein

the indicator lamp drive circuit is configured to receive the first signal outputted by the hard disk state pin, output the first signal to the state indicator lamp in a case that the hard disk is in the non-preset state such that the state indicator lamp flashes, and filter the pulse signal at the second level in a case that the hard disk is in the preset state, so as to output the first control signal at the first level to the state indicator lamp.

18 . The demodulation circuit according to claim 17 , wherein the indicator lamp drive circuit comprises a filter circuit, a fourth amplifier, and a fourteenth resistor;

the filter circuit is connected to the hard disk state pin; an output end of the filter circuit is connected to an input positive end of the fourth amplifier, and an input negative end of the fourth amplifier is connected to its own output end and a first end of the fourteenth resistor, respectively; and a second end of the fourteenth resistor is connected to one end of the state indicator lamp, and the other end of the state indicator lamp is grounded.

19 . The demodulation circuit according to claim 1 , further comprising a buffer circuit, wherein the buffer circuit is respectively connected to the analysis circuit and the sampling control circuit;

the buffer circuit is configured to receive the first signal outputted by the hard disk state pin, buffer the first signal, and output the buffered first signal to the analysis circuit and the sampling control circuit, respectively.

20 . A server, comprising a hard disk, and the demodulation circuit, wherein the demodulation circuit is connected to the hard disk; and

the demodulation circuit comprises a sampling circuit, and a sampling control circuit, wherein the sampling circuit is respectively connected to the analysis circuit and the sampling control circuit;

the analysis circuit is configured to receive a first signal outputted by a hard disk state pin, and analyze a high-level signal and a low-level signal in the first signal, so as to obtain a first pulse width corresponding to the high-level signal and a second pulse width corresponding to the low-level signal, wherein the first signal includes hard disk data;

the sampling control circuit is configured to trigger, according to the first signal, the sampling circuit to sample the first pulse width and the second pulse width such that the hard disk data corresponding to the first signal is analyzed according to the sampled first pulse width and second pulse width, so as to realize the monitoring of a hard disk; and

the demodulation circuit is configured to receive a first signal outputted by a hard disk state pin of the hard disk, and demodulate hard disk log data according to the first signal, so as to realize the monitoring of the hard disk, wherein the first signal comprises hard disk data.