Semiconductor memory device
A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.
1 . A semiconductor storage device comprising:
a memory string including a plurality of memory transistors connected in series;
a plurality of word lines connected to gates of the memory transistors, respectively; and
a control circuit configured to:
in response to a first command set, perform a first read operation; and
in response to a second command set received during the first read operation, perform a second read operation after the first read operation, wherein
during the first read operation, a voltage of a first selected one of the word lines with which data is to be read is decreased from a read pass voltage to a first read voltage, and then increased to the read pass voltage at a first timing,
during the second read operation, a voltage of a second selected one of the word lines with which data is to be read is set to a second read voltage at a second timing later than the first timing, and then increased to the read pass voltage at a third timing later than the second timing, and
voltages of word lines that are neither selected during the first read operation nor the second read operation are maintained from the first timing to the second timing.
2 . The semiconductor storage device according to claim 1 , wherein the voltage of the first selected one of the word lines selected during the first read operation is maintained to be equal to or higher than a first voltage from the first timing to the second timing, the first voltage being one third of the read pass voltage.
3 . The semiconductor storage device according to claim 1 , wherein the first selected one of the word lines is same as the second selected one of the word lines.
4 . The semiconductor storage device according to claim 3 , wherein
the word lines that are neither selected during the first read operation nor the second read operation includes a first non-selected word line directly adjacent to the one of the word lines selected during the first and second read operations and a second non-selected word line that is not directly adjacent to the one of the word lines selected during the first and second read operations,
a voltage of the first non-selected word line is maintained at a first read pass voltage from the first timing to the second timing, and
a voltage of the second non-selected word line is maintained at a second read pass voltage lower than the first read pass voltage from the first timing to the second timing.
5 . The semiconductor storage device according to claim 4 , wherein the read pass voltage is same as one of the first read pass voltage and the second read pass voltage.
6 . The semiconductor storage device according to claim 4 , wherein the read pass voltage is different from the first read pass voltage and the second read pass voltage.
7 . The semiconductor storage device according to claim 1 , wherein the first selected one of the word lines is different from the second selected one of the word lines.
8 . The semiconductor storage device according to claim 1 , wherein
the first read voltage is lower than the second read voltage, and
a first time period to increase the voltage of the first selected one of the word lines from the first read voltage to the read pass voltage during the first read operation is greater than a second time period to increase the voltage of the second selected one of the word lines from the second read voltage to the read pass voltage during the second read operation.
9 . The semiconductor storage device according to claim 1 , wherein
the control circuit is further configured to, in response to a third command set received during the second read operation, perform a third read operation after the second operation,
during the third operation, a voltage of a third selected one of the word lines with which data is to be read is set to a third read voltage at a fourth timing and then increased to the read pass voltage, and
voltages of word lines that are neither selected during the second read operation nor the third read operation are maintained from the third timing to the fourth timing.
10 . The semiconductor storage device according to claim 9 , wherein the voltage of the second selected one of the word lines is maintained at the read pass voltage from the third timing to the fourth timing.
11 . The semiconductor storage device according to claim 1 , wherein the control circuit is further configured to, in response to a third command set received after the second command set during the first read operation, perform a third read operation in accordance with the third command set without performing the second read operation.
12 . The semiconductor storage device according to claim 1 , wherein during the first read operation, the voltage of the first selected one of the word lines is decreased from the read pass voltage to a third read voltage and then further decreased to the first read voltage.
13 . The semiconductor storage device according to claim 1 , wherein during the first read operation, the voltage of the first selected one of the word lines is decreased from the read pass voltage to a third read voltage and then increased to the first read voltage, the first read voltage being lower than the read pass voltage.
14 . The semiconductor storage device according to claim 1 , wherein
the control circuit includes a terminal through which a ready/busy signal is transmitted, a ready state of the ready/busy signal enabling reception of the first and second command sets and a busy state of the ready/busy signal disabling reception of the first and second command sets, and
the control circuit is further configured to set the ready/busy signal to the ready state before the first read voltage is applied to the first selected one of the word lines during the first read operation.
15 . The semiconductor storage device according to claim 14 , wherein the control circuit is further configured to set the ready/busy signal to the busy state upon receiving the second command set during the first read operation.
16 . The semiconductor storage device according to claim 1 , wherein
the control circuit includes a terminal through which a ready/busy signal is transmitted, a ready state of the ready/busy signal enabling reception of the first and second command sets and a busy state of the ready/busy signal disabling reception of the first command set, but enabling reception of the second command set, and
the control circuit is further configured to maintain the ready/busy signal in the busy state during the first read operation.
17 . The semiconductor storage device according to claim 1 , further comprising:
a power supply terminal that receives an operation voltage of the semiconductor storage device, wherein
a first current, which is a maximum current that flows through the power supply terminal during the first read operation, is greater than a second current, which is a maximum current that flows through the power supply terminal during the second read operation.
18 . A method for controlling a semiconductor storage device including:
a memory string including a plurality of memory transistors connected in series; and
a power supply terminal that receives an operation voltage of the semiconductor storage device, the method comprising:
in response to a first command set, performing a first read operation; and
in response to a second command set received during the first read operation, performing a second read operation after the first read operation, wherein
during the first read operation, a voltage of a first selected one of the word lines with which data is to be read is decreased from a read pass voltage to a first read voltage, and then increased to the read pass voltage at a first timing,
during the second read operation, a voltage of a second selected one of the word lines with which data is to be read is set to a second read voltage at a second timing, and then increased to the read pass voltage at a third timing, and
voltages of word lines that are neither selected during the first read operation nor the second read operation are maintained from the first timing to the second timing.
19 . The method according to claim 18 , wherein the voltage of the first selected one of the word lines selected during the first read operation is maintained to be equal to or higher than a first voltage from the first timing to the second timing, the first voltage being one third of the read pass voltage.
20 . The method according to claim 18 , wherein the first selected one of the word lines is same as the second selected one of the word lines.