Physically unclonable function cell and operation method of the same
A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.
1 . A device, comprising:
a physical unclonable function (PUF) cell array comprising a bit cell,
wherein the bit cell comprises:
a transistor coupled to a word line and a source line;
a first memory cell coupled between a first data line and the transistor; and
a second memory cell coupled between the transistor and a second data line different from the first data line.
2 . The device of claim 1 , wherein a resistance of the first memory cell is substantially different from that of the second memory cell.
3 . The device of claim 1 , further comprising:
a sense amplifier configured to compare a voltage level of the first data line with a voltage level of the second data line to generate an output signal, indicating a data state of the bit cell, as a PUF response output.
4 . The device of claim 3 , wherein when the voltage level of the first data line is greater than the voltage level of the second data line, the output signal has a high logic state,
wherein when the voltage level of the second data line is greater than the voltage level of the first data line, the output signal has a low logic state.
5 . The device of claim 1 , wherein in a read operation of the bit cell, a word line voltage at a control terminal of the transistor is different from a read voltage at a first terminal of the transistor coupled to the source line.
6 . The device of claim 5 , wherein a second terminal of the transistor is coupled to the first memory cell and the second memory cell.
7 . The device of claim 1 , wherein in a read operation of the PUF cell array, a magnitude of a first read current flowing through the first memory cell is substantially different from that of a second read current flowing through the second memory cell.
8 . The device of claim 1 , wherein the word line is activated in response to a word line address associated with a challenge input inputted into the PUF cell array.
9 . The device of claim 8 , further comprising:
a first capacitor coupled between the first data line and a ground; and
a second capacitor coupled between the second data line and the ground.
10 . A method, comprising:
discharging a first data line and a second data line to a first voltage before a first memory operation of a bit cell in a physical unclonable function (PUF) cell array;
in the first memory operation of the bit cell, generating a first current to the bit cell according to a second voltage different from the first voltage, and
charging the first and second data lines respectively by a second current generated by a first memory cell and a third current generated by a second memory cell; and
outputting, according to voltages on the first and second data lines, an output signal for generating a PUF response output.
11 . The method of claim 10 , wherein the first voltage is smaller than the second voltage.
12 . The method of claim 10 , wherein outputting, according to voltages on the first and second data lines, the output signal comprises:
sensing the voltage on the first data line being greater than the voltage on the second data line when the second current is greater than the third current.
13 . The method of claim 10 , wherein a resistance of the first memory cell is substantially different from that of the second memory cell.
14 . The method of claim 10 , further comprising:
in a second memory operation of the bit cell, applying a third voltage different from the first voltage and the second voltage to the first data line and the second data line to change a resistance state of the first memory cell from a first resistance state to a second resistance state while a resistance state of the second memory cell remains the first resistance state.
15 . The method of claim 14 , wherein in the second memory operation, the first resistance state is an anti-parallel resistance state of a magnetic tunneling junction, and
the second resistance state is a parallel resistance state of the magnetic tunneling junction.
16 . The method of claim 14 , wherein the third voltage is greater than the first voltage and the second voltage.
17 . A device, comprising:
a bit cell in a physical unclonable function (PUF) cell array, comprising:
a gate structure, a first conductive segments, and a second conductive segment that extend in a first direction and correspond to a transistor;
a first magnetic tunneling junctions (MTJ) structure and a second MTJ structure that are disposed above and coupled to the second conductive segment; and
a first metal line coupled to the first MTJ structure and a second metal line coupled to the second MTJ structure, wherein the first and second metal lines extend in a second direction different from the first direction.
18 . The device of claim 17 , further comprising:
a sense amplifier configured to sense a voltage difference between the first metal line and the second metal line in a read operation to generate a PUF output when a resistance of the first MTJ structure is substantially different from a resistance of the second MTJ structure.
19 . The device of claim 18 , further comprising:
a conductive trace coupled to the first conductive segments and interposed between the first metal line and the second metal line.
20 . The device of claim 17 , further comprising:
a conductive trace coupled to the first conductive segments and interposed between the first metal line and the second metal line,
wherein in a write operation, a voltage of the first metal line and the second metal line is greater than a voltage of the conductive trace.