Memory device performing ECS operation, operation method of the memory device, memory system, electronic device, and electronic system
A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cell rows; a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller.
1 . A memory device comprising:
a memory cell array comprising a plurality of memory cell rows;
a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and
a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller,
wherein the ECS setting data comprises a current value related to a refresh current used in the refresh operation.
2 . The memory device of claim 1 , wherein when a first period value included in first ECS setting data is less than a second period value included in second ECS setting data, a first current value included in the first ECS setting data is greater than a second current value included in the second ECS setting data, and
wherein when the first period value is greater than the second period value, the first current value is less than the second current value.
3 . The memory device of claim 1 , wherein the ECS setting data further comprises data indicating a level of a supply voltage supplied to the memory device in dynamic voltage frequency scaling (DVFS).
4 . The memory device of claim 1 , further comprising:
an error correction code (ECC) circuit configured to perform ECC decoding on data read out from the memory cell array, and output to the control logic circuit an error occurrence signal indicating that an error is present in the data; and
an error counting register,
wherein the control logic circuit is further configured to count the error occurrence signal and store error count data indicating a number of occurrences of errors in the error counting register.
5 . The memory device of claim 4 , wherein the control logic circuit is further configured to provide the ECS setting data and the error count data to the memory controller, in response to a register read command received from the memory controller.
6 . The memory device of claim 5 , wherein the control logic circuit is further configured to:
receive, from the memory controller, new ECS setting data determined according to the number of occurrences of errors, and
store the new ECS setting data in the mode register.
7 . The memory device of claim 6 , wherein the new ECS setting data comprises a new period value indicating a new ECS period at which an ECS operation is performed in the refresh operation and a new current value related to the refresh current used in the refresh operation, and
wherein the memory controller is further configured to determine the new period value and the new current value according to the number of occurrences of errors.