Dynamic random access memory (DRAM) with configurable wordline and bitline voltages
A dynamic random access memory (DRAM) device includes memory core circuitry and power supply circuitry. The memory core circuitry includes an array of DRAM storage cells, with ones of the DRAM storage cells coupled to wordline and bitline power supply busses. The power supply circuitry is coupled to the wordline and bitline power supply busses. The power supply circuitry is responsive to a control signal to generate one of a first set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a first normal mode of operation, or to generate a second set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a second normal mode of operation. A value of the control signal is based on a temperature parameter associated with the DRAM device.
1 . A dynamic random access memory (DRAM) device, comprising:
memory core circuitry including an array of DRAM storage cells, ones of the DRAM storage cells coupled to a wordline power supply bus and a bitline power supply bus;
power supply circuitry coupled to the wordline and bitline power supply busses, responsive to a control signal, to generate a first set of respective wordline and bitline voltages for distribution to the wordline and bitline power supply busses in a first normal mode of operation, or to generate a second set of respective wordline and bitline voltages that is different than the first set of respective wordline and bitline voltages for distribution to the wordline and bitline power supply busses in a second normal mode of operation; and
wherein a value of the control signal is based on a temperature parameter associated with the DRAM device.
2 . The DRAM device of claim 1 , further comprising:
mode control circuitry to generate the control signal.
3 . The DRAM device of claim 2 , wherein the mode control circuitry comprises:
mode register storage to store a mode value that is used to generate the control signal.
4 . The DRAM device of claim 3 , wherein the mode control circuitry is responsive to receipt of a mode register set (MRS) command to initiate storage of the mode value.
5 . The DRAM device of claim 2 , wherein the temperature parameter comprises operating temperature, and the mode control circuitry is responsive to receipt of operating temperature information to generate the control signal.
6 . The DRAM device of claim 5 , wherein the control circuitry further comprises a temperature sensor to generate actual operating temperature information.
7 . The DRAM device of claim 5 , wherein the control circuitry further comprises a sensor input to receive actual operating temperature information from an off-chip temperature sensor.
8 . The DRAM device of claim 5 , wherein the operating temperature information comprises an expected maximum operating temperature value.
9 . The DRAM device of claim 6 , wherein:
the first set of wordline and bitline voltages is higher than the second set of wordline and bitline voltages; and
wherein the first set of wordline and bitline voltages is selected when the temperature information is within a first temperature range, and the second set of wordline and bitline voltages selected when the temperature information is within a second temperature range that is higher than the first temperature range.
10 . The DRAM device of claim 6 , further comprising:
wordline driver circuitry coupled to the power supply circuitry and the wordline power supply bus;
sense amplifier circuitry coupled to the power supply circuitry and the bitline power supply bus;
wherein the power supply circuitry is operative to generate the first set or second set of wordline and bitline voltages for application to the wordline driver circuitry and the sense amplifier circuitry; and
wherein the wordline driver circuitry and the sense amplifier circuitry are operative to distribute the first set or second set of wordline and bitline voltages along the wordline power supply bus and the bitline power supply bus.
11 . An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:
memory core circuitry including an array of DRAM storage cells, ones of the DRAM storage cells coupled to wordline and bitline power supply busses;
wherein for a first normal mode of operation, the wordline and bitline power supply busses supply a first predetermined set of wordline and bitline voltages to the DRAM storage cells; and
wherein for a second normal mode of operation, the wordline and bitline power supply busses supply a second predetermined set of wordline and bitline voltages that is different than the first predetermined set of wordline and bitline voltages to the DRAM storage cells; and
mode control circuitry to generate a mode control signal to control a selection between the first and second normal modes of operation based on a temperature parameter associated with the IC DRAM device.
12 . The IC DRAM device of claim 11 , wherein the mode control circuitry further comprises:
mode register storage to store a mode value that is used to generate the mode control signal.
13 . The IC DRAM device of claim 12 , wherein the mode control circuitry is responsive to receipt of a mode register set (MRS) command to initiate storage of the mode value.
14 . The IC DRAM device of claim 11 , wherein the temperature parameter comprises operating temperature, and the mode control circuitry is responsive to receipt of operating temperature information to generate the control signal.
15 . The IC DRAM device of claim 14 , wherein the mode control circuitry further comprises a temperature sensor to generate operating temperature information.
16 . The IC DRAM device of claim 14 , wherein the mode control circuitry further comprises a sensor input to receive operating temperature information from an off-chip temperature sensor.
17 . A method of operation in a dynamic random access memory (DRAM) device, the method comprising:
storing data in an array of DRAM storage cells, ones of the DRAM storage cells coupled to wordline and bitline power supply busses;
generating, in response to a first value of a control signal, one of a first set of predefined wordline and bitline voltages for application to the wordline and bitline power supply busses in a first normal mode of operation;
generating, in response to a second value of the control signal, a second set of predefined wordline and bitline voltages that is different than the first set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a second normal mode of operation; and
controlling the value of the control signal based on a temperature parameter associated with the DRAM device.
18 . The method of claim 17 , further comprising:
storing a mode value that is used to generate the control signal in mode register storage.
19 . The method of claim 18 , further comprising:
initiating storage of the mode value in response to receipt of a mode register set (MRS) command.
20 . The method of claim 19 , further comprising:
generating the control signal based on receipt of operating temperature information.