Memory physical layer interface, memory apparatus and method thereof

1 . A memory apparatus, comprising:

a memory device;

a memory controller; and

a memory physical layer interface, coupled between the memory device and the memory controller, the memory physical layer interface comprises:

a multi-tap decision feedback equalization (DFE) receiver, comprising a plurality of DFE taps; and

a tap reset circuit, generating a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset the plurality of DFE taps during the gap interval between the read bursts,

wherein the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval, the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval, and the second predetermined interval is greater than the first predetermined interval.

2 . The memory apparatus of claim 1 , wherein

the memory physical layer interface further comprises a digital logic connected to the tap reset circuit, and

the tap reset circuit comprises:

a first serializer, receiving a first input signal from the digital logic, generating a first serial signal in accordance with the first input signal;

a first delay circuit, connected to the first serializer, delaying the first serial signal to generate a first delayed serial signal, and

a first buffer, connected to the first delay circuit, generating the pulse signal in accordance with the first delayed serial signal.

3 . The memory apparatus of claim 2 , wherein the tap reset circuit further comprises:

a second serializer, receiving a second input signal from the digital logic, generating a second serial signal in accordance with the second input signal;

a second delay circuit, connected to the second serializer, delaying the second serial signal to generate a second delayed serial signal; and

a second buffer, connected to the second delay circuit, generating the reset signal in accordance with the second delayed serial signal.

4 . The memory apparatus of claim 1 , wherein

the first predetermined interval is one-cycle interval, and

the second predetermined interval is n-cycle interval, wherein n is an integer greater than or equal to 2.

5 . The memory apparatus of claim 1 , wherein the memory physical layer interface further comprises:

a gated clock generating circuit, receiving an internal enable signal and a read enable signal from the memory controller, and generating a gated clock signal in accordance with the internal enable signal and the read enable signal.

6 . The memory apparatus of claim 5 , wherein the gated clock generating circuit comprises:

a receiver, receiving the internal enable signal and data strobe signals, generating a first signal in accordance with the internal enable signal and the data strobe signals;

a gate generation circuit, receiving the read enable signal and generating a gate enable signal in accordance with the read enable signal;

a logic gate, coupled to the receiver and the gate generation circuit, receiving the first signal and the gate enable signal, generating a second signal in accordance with the first signal and the gate enable signal;

a digitally controlled delay line, coupled to the first logic gate, delaying the second signal to generate a third signal;

a duty-cycle corrector, delaying the third signal to generate a fourth signal; and

a buffer, outputting the gated clock signal in accordance with the fourth signal.

7 . The memory apparatus of claim 5 , wherein the memory physical layer interface further comprises:

a training logic, coupled to the gated clock generating circuit and the tap reset circuit, receiving the gated clock signal, the pulse signal, and the reset signal, performing a training process to align the pulse signal and the pulse signal with the gated clock signal.

8 . The memory apparatus of claim 7 , wherein

the training logic is configured to adjust delay amount of the pulse signal until the pulse signal aligns to the gated clock signal, and

the training logic is configured to adjust delay amount of the reset signal until the pulse signal aligns to the gated clock signal.

9 . The memory apparatus of claim 8 , wherein the memory physical layer interface further comprises:

a first delay element, delaying the gated clock signal to generate a delayed clock signal;

a second delay element, delaying the pulse signal to generate a delayed pulse signal;

a third second delay element, delaying the reset signal to generate a tap reset signal;

a logic gate, coupled to the first delay element and the second delay element, performing a logic operation on the delayed clock signal and the delayed pulse signal to generate a sample clock signal.

10 . The memory apparatus of claim 9 ,

wherein the multi-tap DFE receiver is configured to receive a data signal, a reference voltage, the tap reset signal, the sample clock signal and the internal enable signal,

the multi-tap DFE receiver is configured to generate an output data in accordance with the data signal, the reference voltage, the tap reset signal, the sample clock signal and the internal enable signal.

11 . A memory physical layer interface, comprising:

a multi-tap decision feedback equalization (DFE) receiver, comprising a plurality of DFE taps; and

a tap reset circuit, generating a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset the plurality of DFE taps during the gap interval between the read bursts,

wherein the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval, the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval, and the second predetermined interval is greater than the first predetermined interval.

12 . The memory physical layer interface of claim 11 , wherein

the memory physical layer interface further comprises a digital logic connected to the tap reset circuit, and

the tap reset circuit comprises:

a first serializer, receiving a first input signal from the digital logic, generating a first serial signal in accordance with the first input signal;

a second serializer, receiving a second input signal from the digital logic, generating a second serial signal in accordance with the second input signal;

a first delay circuit, connected to the first serializer, delaying the first serial signal to generate a first delayed serial signal;

a second delay circuit, connected to the second serializer, delaying the second serial signal to generate a second delayed serial signal;

a first buffer, connected to the first delay circuit, generating the pulse signal in accordance with the first delayed serial signal; and

a second buffer, connected to the second delay circuit, generating the reset signal in accordance with the second delayed serial signal.

13 . The memory physical layer interface of claim 11 , wherein

the first predetermined interval is one-cycle interval, and

the second predetermined interval is n-cycle interval, wherein n is an integer greater than or equal to 2.

14 . The memory physical layer interface of claim 11 , further comprising:

a training logic, receiving a gated clock signal, the pulse signal and the reset signal, performing a training process to align the pulse signal and the pulse signal with the gated clock signal, wherein

the training logic is configured to adjust delay amount of the pulse signal until the pulse signal aligns to the gated clock signal, and the training logic is configured to adjust delay amount of the reset signal until the pulse signal aligns to the gated clock signal.

15 . The memory physical layer interface of claim 14 , further comprising:

a first delay element, delaying the gated clock signal to generate a delayed clock signal;

a second delay element, delaying the pulse signal to generate a delayed pulse signal;

a third second delay element, delaying the reset signal to generate a tap reset signal;

a logic gate, coupled to the first delay element and the second delay element, performing a logic operation on the delayed clock signal and the delayed pulse signal to generate a sample clock signal.

16 . A method of a memory apparatus comprising a memory device, a memory controller and a memory physical layer interface, the memory physical layer interface comprising a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit, the method comprising:

generating a pulse signal and a reset signal in accordance with a gap interval between read bursts;

resetting a plurality of DFE taps of the muti-tap DFE receiver using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval; and

resetting the plurality of DFE taps of the muti-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval,

wherein the second predetermined interval is greater than the first predetermined interval.

17 . The method of claim 16 , wherein generating the pulse signal in accordance with the gap interval between read bursts comprises:

generating, by a first serializer of the tap reset circuit, a first serial signal in accordance with a first input signal received from a digital logic of the memory physical layer interface;

generating, by a second serializer of the tap reset circuit, a second serial signal in accordance with the second input signal received from the digital logic of the memory physical layer interface;

delaying, by a first delay circuit of the tap reset circuit, the first serial signal to generate a first delayed serial signal;

delaying, by a second delay circuit of the tap reset circuit, the second serial signal to generate a second delayed serial signal; and

generating, by a first buffer of the tap reset circuit, the pulse signal in accordance with the first delayed serial signal; and

generating, by a second buffer of the tap reset circuit, the reset signal in accordance with the second delayed serial signal.

18 . The method of claim 16 , wherein

the first predetermined interval is one-cycle interval, and

the second predetermined interval is n-cycle interval, wherein n is an integer greater than or equal to 2.

19 . The method of claim 18 , further comprising:

receiving, by a training logic of the memory physical layer interface, the gated clock signal, the pulse signal and the reset signal; and

performing, by the training logic of the memory physical layer interface, a training process to align the pulse signal and the pulse signal with the gated clock signal,

wherein the training logic is configured to adjust delay amount of the pulse signal until the pulse signal aligns to the gated clock signal, and the training logic is configured to adjust delay amount of the reset signal until the pulse signal aligns to the gated clock signal.

20 . The method of claim 19 , further comprising:

delaying, by a first delay element of the memory physical layer interface, the gated clock signal to generate a delayed clock signal;

delaying, by a second delay element of the memory physical layer interface, the pulse signal to generate a delayed pulse signal;

delaying, by a third second delay element of the memory physical layer interface, the reset signal to generate a tap reset signal; and

performing, by a logic gate of the memory physical layer interface, a logic operation on the delayed clock signal and the delayed pulse signal to generate a sample clock signal.