Semiconductor device having row decoder circuit
An example apparatus includes first and second memory cell arrays arranged in a first direction; and a plurality of first and second sub word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each arranged on an intermediate region between the first and second memory cell arrays. The first and second sub word line drivers are arranged in a second direction and along the first and second memory cell array, respectively. The main word line drivers are arranged in the second direction and adjacently along the plurality of second sub word line drivers. The level shift circuits are arranged in the second direction and adjacently along the plurality of first sub word line drivers. The level shift circuits are configured to provide voltage-level-shifted signals to the plurality of main word line drivers, respectively.
1 . An apparatus comprising:
a first memory cell array;
a second memory cell array, the second memory cell array and the first memory cell array being arranged in a first direction;
a plurality of first sub word line drivers and a plurality of second sub word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each arranged on an intermediate region between the first memory cell array and the second memory cell array,
wherein the plurality of first sub word line drivers are arranged in a second direction perpendicular to the first direction and along the first memory cell array,
wherein the plurality of second sub word line drivers are arranged in the second direction and along the second memory cell array,
wherein the plurality of main word line drivers are arranged in the second direction and adjacently along the plurality of second sub word line drivers, and
wherein the plurality of level shift circuits are arranged in the second direction and adjacently along the plurality of first sub word line drivers, the plurality of level shift circuits being configured to provide voltage-level-shifted signals to the plurality of main word line drivers, respectively.
2 . The apparatus of claim 1 ,
wherein the intermediate region includes a first circuit region on which the plurality of level shift circuits are arranged,
wherein the first circuit region includes a first transistor region of a first conductivity type and a second transistor region of a second conductivity type opposite to the first conductivity type, and
wherein the first transistor region and the second transistor region are arranged in the first direction.
3 . The apparatus of claim 2 ,
wherein the intermediate region further includes a first sub word driver region on which the plurality of first sub word line drivers are arranged,
wherein the first sub word driver region includes a third transistor region having the first conductivity type and a fourth transistor region having the second conductivity type, and
wherein the third transistor region and the fourth transistor region are arranged in the first direction.
4 . The apparatus of claim 3 , wherein the first transistor region and the third transistor region are integrated.
5 . The apparatus of claim 4 ,
wherein the intermediate region includes a second circuit region on which the plurality of main word line drivers are arranged,
wherein the second circuit region includes a fifth transistor region of the first conductivity type and a sixth transistor region of the second conductivity type, and
wherein the fifth transistor region and the sixth transistor region are arranged in the first direction.
6 . The apparatus of claim 5 ,
wherein the intermediate region further includes a second sub word driver region on which the plurality of second sub word line drivers are arranged,
wherein the second sub word driver region includes a seventh transistor region having the first conductivity type and an eighth transistor region having the second conductivity type, and
wherein the seventh transistor region and the eighth transistor region are arranged in the first direction.
7 . The apparatus of claim 6 , wherein the fifth transistor region and the seventh transistor region are integrated.
8 . The apparatus of claim 7 , further comprising:
a plurality of word selection circuits each configured to generate an associated one of a plurality of word selection signals; and
a plurality of word selection lines supplied with an associated one of the plurality of word selection signals and extending in the first direction so as to overlap the first and second memory cell arrays,
wherein the intermediate region further includes a third circuit region arranged between the first and second circuit regions in the first direction, and
wherein the plurality of word selection circuits are arranged on the third circuit region.
9 . The apparatus of claim 8 , further comprising a first signal line supplying one of the voltage-level-shifted signals from one of the plurality of level shift circuits to one of the plurality of main word line drivers,
wherein the first signal line extends in the first direction so as to be across the third circuit region.
10 . The apparatus of claim 8 , further comprising a sense amplifier region on which a plurality of sense amplifiers are arranged,
wherein the first memory cell array further includes a bit line coupled to an associated one of the plurality of sense amplifiers and a memory cell coupled to a first sub word line and the bit line.
11 . The apparatus of claim 10 , further comprising a plurality of bit selection circuits configured to control the plurality of sense amplifiers,
wherein the intermediate region further includes a fourth circuit region arranged between the first and second circuit regions in the first direction, and
wherein the plurality of bit selection circuits are arranged on the fourth region.
12 . The apparatus of claim 11 , wherein the third and fourth regions are arranged in second direction perpendicular to the first direction.
13 . The apparatus of claim 11 , further comprising a second signal line supplying another one of the voltage-level-shifted signals from another one of the plurality of level shift circuits to one of the plurality of main word line drivers,
wherein the second signal line extends in the first direction so as to be across the fourth circuit region.
14 . The apparatus of claim 7 , further comprising a plurality of additional level shift circuits arranged between the second circuit region and the third and fourth circuit regions.